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参数资料
型号： MC68HC908RK2DW
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO20
封装： PLASTIC, SOIC-20
文件页数： 96/158页
文件大小： 1020K
代理商： MC68HC908RK2DW
Configuration Register (CONFIG)
MC68HC908RK2 Data Sheet, Rev. 5.1
42
Freescale Semiconductor
LVISTOP — LVI Enable in Stop Mode Bit
When the LVIPWR bit is set, setting the LVISTOP bit enables the LVI to operate during stop mode.
Reset clears LVISTOP.
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
LVIRST — LVI Reset Enable Bit
LVIRST enables the reset signal from the LVI module. See Chapter 8 Low-Voltage Inhibit (LVI).
1 = LVI module resets enabled
0 = LVI module resets disabled
LVIPWR — LVI Power Enable Bit
LVIPWR disables the LVI module. See Chapter 8 Low-Voltage Inhibit (LVI).
1 = LVI module power enabled
0 = LVI module power disabled
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS. See Chapter 4 Computer Operating
Properly Module (COP).
1 = COP timeout period = 213 – 24 CGMXCLK cycles
0 = COP timeout period = 218 – 24 CGMXCLK cycles
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a
4096-CGMXCLK cycle delay.
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLK cycles
NOTE
Exiting stop mode by pulling reset will result in the long stop recovery.
If using the internal clock generator module or an external crystal oscillator,
do not set the SSREC bit.
The LVI has an enable time of ten. The system stabilization time for
power-on reset and long stop recovery (both 4096 CGMXCLK cycles) gives
a delay longer than the LVI enable time for these startup scenarios. There
is no period where the MCU is not protected from a low power condition.
However, when using the short stop recovery configuration option, the 32
CGMXCLK delay must be greater than the LVI’s turn on time to avoid a
period in startup where the LVI is not protecting the MCU.
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. See Chapter 4 Computer Operating Properly Module (COP).
1 = COP module disabled
0 = COP module enabled
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