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参数资料
| 型号： | MC7455ARX867LG |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 867 MHz, RISC PROCESSOR, CBGA483 |
| 封装： | 29 X 29 MM, 1.27 MM PITCH, CERAMIC, BGA-483 |
| 文件页数： | 19/76页 |
| 文件大小： | 1520K |
| 代理商： | MC7455ARX867LG |
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26
MPC7455 RISC Microprocessor Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
Figure 10 shows the L3 bus timing diagrams for the MPC7455 interfaced to MSUG2 SRAMs.
Figure 10. L3 Bus Timing Diagrams for L3 Cache DDR SRAMs
1.5.2.4.2
L3 Bus AC Specifications for PB2 and Late Write SRAMs
When using PB2 or late write SRAMs at the L3 interface, the parts should be connected as shown in
Figure 11. These SRAMs are synchronous to the MPC7455; one L3_CLKn signal is output to each SRAM
to latch address, control, and write data. Read data is launched by the SRAM synchronous to the delayed
L3_CLKn signal it received. The MPC7455 needs a copy of that delayed clock which launched the SRAM
read data to know when the returning data will be valid. Therefore, L3_ECHO_CLK1 and
L3_ECHO_CLK3 must be routed halfway to the SRAMs and then returned to the MPC7455 inputs
L3_ECHO_CLK0 and L3_ECHO_CLK2, respectively. Thus, L3_ECHO_CLK0 and L3_ECHO_CLK2 are
phase-aligned with the input clock received at the SRAMs. The MPC7455 will latch the incoming data on
the rising edge of L3_ECHO_CLK0 and L3_ECHO_CLK2.
Table 13 provides the L3 bus interface AC timing specifications for the configuration shown in Figure 11,
assuming the timing relationships of Figure 12 and the loading of Figure 8.
L3_ECHO_CLK[0,1,2,3]
L3 Data and Data
VM
VM = Midpoint Voltage (GVDD/2)
Parity Inputs
L3_CLK[0,1]
ADDR, L3CNTL
VM
tL3CHOV
tL3CHOX
VM
L3DATA WRITE
tL3CHOZ
VM
tL3CHDV
tL3CHDX
VM
Outputs
Inputs
tL3CLDV
tL3CLDX
tL3CLDZ
tL3DVEH
tL3DXEL
tL3DVEL
tL3DXEH
Note: tL3DVEH and tL3DVEL as drawn here will be negative numbers, that is, input setup time will be
time after the clock edge.
Note: tL3CHDV and tL3CLDV as drawn here will be negative numbers, that is, output valid time will be
time before the clock edge.
VM = Midpoint Voltage (GVDD/2)
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| MC7457RX1000LC | 功能描述:微处理器 - MPU APOLO7 RV1.2 1.3V 105C RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MC7457RX1000NB | 制造商:Motorola Inc 功能描述: |
| MC7457RX1000NC | 功能描述:微处理器 - MPU APOLO7 RV1.2 1.1V 105C RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
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