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参数资料
| 型号： | MC7455ARX867LG |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 867 MHz, RISC PROCESSOR, CBGA483 |
| 封装： | 29 X 29 MM, 1.27 MM PITCH, CERAMIC, BGA-483 |
| 文件页数： | 3/76页 |
| 文件大小： | 1520K |
| 代理商： | MC7455ARX867LG |
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MOTOROLA
MPC7455 RISC Microprocessor Hardware Specifications
11
Electrical and Thermal Characteristics
Figure 2 shows the undershoot and overshoot voltage on the MPC7455.
Figure 2. Overshoot/Undershoot Voltage
The MPC7455 provides several I/O voltages to support both compatibility with existing systems and
migration to future systems. The MPC7455 core voltage must always be provided at nominal 1.3 V (see
Table 4 for actual recommended core voltage). Voltage to the L3 I/Os and processor interface I/Os are
provided through separate sets of supply pins and may be provided at the voltages shown in Table 3. The
input voltage threshold for each bus is selected by sampling the state of the voltage select pins at the
negation of the signal HRESET. The output voltage will swing from GND to the maximum voltage applied
to the OVDD or GVDD power pins.
Storage temperature range
Tstg
–55 to 150
°C
Notes:
1.
Functional and tested operating conditions are given in Table 4. Absolute maximum ratings are stress ratings
only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect
device reliability or cause permanent damage to the device.
2.
Caution: Vin must not exceed OVDD or GVDD by more than 0.3 V at any time including during power-on reset.
3.
Caution: OVDD/GVDD must not exceed VDD/AVDD by more than 2.0 V during normal operation; this limit may be
exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
4.
Caution: VDD/AVDD must not exceed OVDD/GVDD by more than 1.0 V during normal operation; this limit may be
exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
5.
Vin may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
6.
BVSEL must be set to 0, such that the bus is in 1.8 V mode.
7.
BVSEL must be set to HRESET or 1, such that the bus is in 2.5 V mode.
8.
L3VSEL must be set to HRESET (inverse of HRESET), such that the bus is in 1.5 V mode.
9.
L3VSEL must be set to 0, such that the bus is in 1.8 V mode.
10. L3VSEL must be set to HRESET or 1, such that the bus is in 2.5 V mode.
Table 2. Absolute Maximum Ratings 1 (continued)
Characteristic
Symbol
Maximum Value
Unit
Notes
VIH
GND
GND – 0.3 V
GND – 0.7 V
Not to Exceed 10%
OVDD/GVDD + 20%
VIL
OVDD/GVDD
OVDD/GVDD + 5%
of tSYSCLK
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