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参数资料
| 型号： | MC88915TFN160R2 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28 |
| 封装： | PLASTIC, LCC-28 |
| 文件页数： | 19/19页 |
| 文件大小： | 181K |
| 代理商： | MC88915TFN160R2 |
MC88915T
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
20
MC88915TFN133 (continued)
AC CHARACTERISTICS (TA =–40° C to +85° C, VCC = 5.0V ±5%, Load = 50 Terminated to VCC/2)
Symbol
Parameter
Min
Max
Unit
Condition
tRISE/FALL
Outputs
Rise/Fall Time, All Outputs
(Between 0.2VCC and 0.8VCC)
1.0
2.5
ns
Into a 50
Load
Terminated to VCC/2
tRISE/FALL1
2X_Q Output
Rise/Fall Time Into a 20pF Load, With
Termination Specified in Note 2
0.5
1.6
ns
tRISE: 0.8V – 2.0V
tFALL: 2.0V – 0.8V
tPULSE WIDTH1
(Q0–Q4, Q5, Q/2)
Output Pulse Width: Q0, Q1, Q2, Q3,
Q4, Q5, Q/2 @ VCC/2
0.5tCYCLE – 0.5 2
0.5tCYCLE + 0.5 2
ns
Into a 50
Load
Terminated to VCC/2
tPULSE WIDTH1
(2X_Q Output)
Output Pulse Width:
66–133MHz
2X_Q @ 1.5V
40–65MHz
0.5tCYCLE – 0.5 2
0.5tCYCLE – 0.9
0.5tCYCLE + 0.5 2
0.5tCYCLE + 0.9
ns
Must Use Termination
Specified in Note 2
tPULSE WIDTH1
(2X_Q Output)
Output Pulse Width:
66–133MHz
2X_Q @ VCC/2
40–65MHz
0.5tCYCLE – 0.5 2
0.5tCYCLE – 0.9
0.5tCYCLE + 0.5 2
0.5tCYCLE + 0.9
ns
Into a 50
Load
Terminated to VCC/2
tPD 1,3
SYNC F
db
k
SYNC Input to Feedback Delay
(M
d t SYNC0
1
d
(With 1M
from RC1 to An VCC)
ns
See Note 4 and
Fi
2 f
Dtild
SYNC Feedback
(Measured at SYNC0 or 1 and
FEEDBACK Input Pins)
–1.05
–0.25
Figure 2 for Detailed
Explanation
FEEDBACK Input Pins)
(With 1M
from RC1 to An GND)
Explanation
+1.25
+3.25
tSKEWr 1,4
(Rising) See Note 5
Output–to–Output Skew Between Out-
puts Q0–Q4, Q/2 (Rising Edges Only)
—
500
ps
All Outputs Into a
Matched 50
Load
Terminated to VCC/2
tSKEWf 1,4
(Falling)
Output–to–Output Skew Between Out-
puts Q0–Q4 (Falling Edges Only)
—
500
ps
All Outputs Into a
Matched 50
Load
Terminated to VCC/2
tSKEWall1,4
Output–to–Output Skew 2X_Q, Q/2,
Q0–Q4 Rising, Q5 Falling
—
750
ps
All Outputs Into a
Matched 50
Load
Terminated to VCC/2
tLOCK5
Time Required to Acquire Phase–Lock
From Time SYNC Input Signal is
Received
1.0
10
ms
Also Time to LOCK
Indicator High
tPZL6
Output Enable Time OE/RST to 2X_Q,
Q0–Q4, Q5, and Q/2
3.0
14
ns
Measured With the
PLL_EN Pin Low
tPHZ,tPLZ6
Output Disable Time OE/RST to 2X_Q,
Q0–Q4, Q5, and Q/2
3.0
14
ns
Measured With the
PLL_EN Pin Low
1. These specifications are not tested, they are guaranteed by statistcal characterization. See AC specification Note 1.
2. TCYCLE in this spec is 1/Frequency at which the particular output is running.
3. The TPD specification’s min/max values may shift closer to zero if a larger pullup resistor is used.
4. Under equally loaded conditions and at a fixed temperature and voltage.
5. With VCC fully powered–on, and an output properly connected to the FEEDBACK pin. tLOCK maximum is with C1 = 0.1F, tLOCK minimum is
with C1 = 0.01
F.
6. The tPZL, tPHZ, tPLZ minimum and maximum specifications are estimates, the final guaranteed values will be available when ‘MC’ status is
reached.
2
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