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| 型号： | MCZ33781EK |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 10/44页 |
| 文件大小： | 0K |
| 描述： | IC MASTER DSI 2.02 DIFF 32-SOIC |
| 标准包装： | 42 |
| 应用： | 车载系统 |
| 接口： | SPI |
| 电源电压： | 4.75 V ~ 5.25 V |
| 封装/外壳： | 32-BSOP（0.295"，7.50mm 宽）裸露焊盘 |
| 供应商设备封装： | 32-SOICW 裸露焊盘 |
| 包装： | 管件 |
| 安装类型： | 表面贴装 |
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Analog Integrated Circuit Device Data
18
Freescale Semiconductor
33781
FUNCTIONAL DESCRIPTIONS
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
VSUPn VOLTAGE MONITOR
This function monitors the voltage on the VSUPn pin. If the
voltage on the pin drops below the defined voltage threshold
for longer than the voltage threshold mask time, the 33781
will continue to send queued DBUS commands, but not set
any RNE bits in the DnSTAT registers to 1, until either the
device is reset by the RST pin or the EN bits in the DnEN
registers are first set to zero, and then to one (disabled and
then enabled). By monitoring the RNE bits the MCU will know
that communications have been disrupted and can take the
appropriate action.
Figure 11. Driver/Receiver Block Diagram
DBUS DRIVER /RECEIVER (PHYSICAL LAYER)
There are four independent differential bus driver/receiver
blocks on the 33781. These blocks translate the transmit data
to the voltage and current needed to drive the DBUS. They
also detect the response current from the slave devices and
translate that current into digital levels. These circuits can
drive their outputs to the levels listed in Table 5.
The DBUS driver/receiver block diagram is shown in
Figure 11. The circuit uses a common driver for both the Idle
and Signal modes to minimize common mode noise. The
drivers are disabled in HiZ.
During Idle mode the driver is required to supply a high
current to recharge the Slave device storage capacitors. In
both Idle and Signal modes it is required to drive the DBUS
load capacitances and control the slew rate over a wide
supply voltage range and load conditions. Current limit, over-
current shutdown and thermal shutdown are included to
protect the device from fault conditions. More information can
be found in the Protection and Diagnostic Features and SPI0
Register and Bit Descriptions sections.
To ensure stability of the bus drivers, capacitors must be
connected between each output and ground. These are the
DBUS common mode capacitors. In addition, a bypass
capacitor is required at VSUPn. These capacitors must be
located close to the IC Pins and provide a low-impedance
path to ground.
The internal signal DSIF controls the Idle to Signalling
state change, and internal signal DSIS controls the signal
level, high or low. DSIR is the slave device response signal to
the logic. This is shown in Table 6.
Bus wire faults on a bus do not disrupt communications on
another bus. In addition, each bus channel has independent
thermal shutdown protection. Once the channel thermal limit
is reached the bus drivers become high-impedance, the TS
bit is set to a 1 and the EN bit set to 0 in the channel DEN
register. In addition the channel address buffer registers and
pointers are reset. There is a 4 usec filter on Tlim to prevent
false triggering.
The Differential Signal Generation block converts the
DSIS signal to the DBUS differential signal voltage levels.
This differential signal is buffered and slew rate controlled by
Differential
Signal
Generation
DSISn
DSIFn
hiZn
Common
Mode
Correction
Adder
Receiver Low n
Receiver High n
Receiver Sum n
Over Current
Over Temp
Sense
Signal Mode Over Current n
Idle Mode Over Current n
Over Temp n
DnH
DnL
Driver
Overvoltage
Over-current
Over-temp n
Over-temp
Over-voltage
Over-current
Receiver Low n
Receiver High n
Receiver Sum n
Sense
Adder
DSISn
DSIFn
hiZn
Differential
Signal
Generation
Common
Mode
Correction
DnH
DnL
Idle Mode Over-current n
Signal Mode Over-current n
Over-temp n
Driver
Table 6. Internal Signal Truth Table
DSIF
DSIS
TS
DSIR
DnD
0
Return Data
Signal Low
0
1
0
Return Data
Signal High
1
0
High-impedance
11
0
Idle
X
1
0
High-impedance
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MCZ33781EKR2 | 功能描述:输入/输出控制器接口集成电路 DBUS2 MASTER STND RoHS:否 制造商:Silicon Labs 产品: 输入/输出端数量: 工作电源电压: 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:QFN-64 封装:Tray |
| MCZ33784EF | 功能描述:加速计 - 板上安装 DBUS2 SENSOR INTERFACE RoHS:否 制造商:Murata 传感轴:Double 加速:12 g 灵敏度: 封装 / 箱体: 输出类型:Analog 数字输出 - 位数:11 bit 电源电压-最大:5.25 V 电源电压-最小:4.75 V 电源电流:4 mA 最大工作温度:+ 125 C 最小工作温度:- 40 C |
| MCZ33784EF/R2- | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:DSI 2.02 Sensor Interface |
| MCZ33784EFR2 | 功能描述:加速计 - 板上安装 DBUS2 SENSOR INTERFACE RoHS:否 制造商:Murata 传感轴:Double 加速:12 g 灵敏度: 封装 / 箱体: 输出类型:Analog 数字输出 - 位数:11 bit 电源电压-最大:5.25 V 电源电压-最小:4.75 V 电源电流:4 mA 最大工作温度:+ 125 C 最小工作温度:- 40 C |
| MCZ33789AE | 功能描述:网络控制器与处理器 IC Airbag ASSP RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
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