参数资料
型号: MCZ33905S5EK
厂商: Freescale Semiconductor
文件页数: 60/106页
文件大小: 0K
描述: IC SYSTEM BASIS CHIP GEN2 32SOIC
标准包装: 42
应用: 系统基础芯片
接口: CAN,LIN
电源电压: 5.5 V ~ 27 V
封装/外壳: 32-BSOP(0.295",7.50mm 宽)裸露焊盘
供应商设备封装: 32-SOICW 裸露焊盘
包装: 管件
安装类型: 表面贴装
Analog Integrated Circuit Device Data
Freescale Semiconductor
57
33903/4/5
CAN INTERFACE
CAN INTERFACE DESCRIPTION
Figure 35. Single Dominant Pulse Wake-up
Pattern Wake-up
In order to Wake-up the CAN interface, the Wake-up
receiver must receive a series of three consecutive valid
dominant pulses, by default when the CANWU bit is low.
CANWU bit can be set high by SPI and the Wake-up will occur
after a single pulse duration of 2.0
s (typically).
A valid dominant pulse should be longer than 500 ns. The
three pulses should occur in a time frame of 120
s, to be
considered valid. When three pulses meet these conditions,
the wake signal is detected. This is illustrated by the following
figure.
.
Figure 36. Pattern Wake-up - Multiple Dominant Detection
BUS TERMINATION
The device supports the two main types of bus
terminations:
Differential termination resistors between CANH and
CANL lines.
SPLIT termination concept, with the mid point of the
differential termination connected to GND through a
capacitor and to the SPLIT pin.
In application, the device can also be used without
termination.
Figure 37 illustrates some of the most common
terminations.
CANL
CANH
Internal Wake-up signal
Dominant
CAN
Pulse # 1
Dominant
Pulse # 2
tCAN WU1-F
Can Wake-up detected
bus
Internal differential Wake-up receiver signal
CANL
CANH
Internal Wake-up signal
Dominant
Internal differential Wake-up receiver signal
CAN
Pulse # 1
Dominant
Pulse # 2
Dominant
Pulse # 3
Dominant
Pulse # 4
tCAN WU3-F
tCAN WU3-TO
Dominant Pulse # n: duration 1 or multiple dominant bits
Can Wake-up detected
bus
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