参数资料
型号: ML60851EGA
厂商: OKI ELECTRIC INDUSTRY CO LTD
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP44
封装: 0.80 MM PITCH, PLASTIC, QFP-44
文件页数: 28/88页
文件大小: 1137K
代理商: ML60851EGA
Oki Semiconductor
ML60851E
32/84
DMA Interval Register (DMAINTVL)
Read address
DEh
Write address
5Eh
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
After a bus reset
The previous value is retained
Definition
Interval time
This register is used for specifying the interval of the single DMA transfer mode, that is, the interval from the
completion of the previous byte (or word) DMA transfer until DREQ is asserted again. The time per bit is 84 ns
(12 MHz, one period).
Interval time = (DREQ enable time) + 84 x n (ns)
See DMA timings (1), (2), (5), and (6) for details of the DREQ enable time.
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