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参数资料
| 型号： | ML60851EGA |
| 厂商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| 封装： | 0.80 MM PITCH, PLASTIC, QFP-44 |
| 文件页数： | 68/88页 |
| 文件大小： | 1137K |
| 代理商： | ML60851EGA |
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Oki Semiconductor
ML60851E
68/84
(3) EP0 Transmit packet ready interrupt
This is used mainly during the transmission of a data packet in a control read transfer.
Operation
Source of operation
Description (conditions, responses, etc.)
EP0 Transmit packet ready
interrupt generation
ML60851E
The EP0 transmit packet ready bit (D4 of PKTRDY) is
de-asserted during a control read transfer when the
processing has changed from the setup stage to the data
stage, and it is possible to write the transmit data to the
FIFO.
At this time, an interrupt is generated if the EP0 transmit
packet ready interrupt enable bit (bit D4 of INTENBL) has
been asserted.
For the second and subsequent packets, in addition to this
condition, before the interrupt is generated, it is necessary
for an ACK response to come from the host for the packet
that has just been sent.
End of EP0 transmit packet
ready interrupt
Local MCU (firmware)
In the case of EP0 transmission, after the one packet of the
EP0 transmit data has been written in EP0TXFIFO, write a
“1” into the EP0 transmit packet ready bit (bit D4 of
PKTRDY). This puts the ML60851E in a state in which it
can transmit the data (that is, it can transmit the data packet
when an IN token arrives), and the
INTR pin is de-asserted
at the same time.
Even when the number of bytes in the write data is less
than the maximum packet size, it is possible to transmit the
data by writing a “1” into the transmit packet ready status
bit. This makes it possible to transmit a short packet.
The following table outlines the relationship between ML60851E registers and EP0 transmit packet ready interrupt
generation.
INTENBL(D4)
EP0 Tx PKTRDY(D4)
INTSTAT(D4)
1
0
1
0
X
0
X This symbol means that it does not matter whether the value is ‘1’ or ‘0’
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相关代理商/技术参数 |
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