参数资料
型号: ML60851EGA
厂商: OKI ELECTRIC INDUSTRY CO LTD
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP44
封装: 0.80 MM PITCH, PLASTIC, QFP-44
文件页数: 36/88页
文件大小: 1137K
代理商: ML60851EGA
Oki Semiconductor
ML60851E
39/84
End Point 0 Status Register (EP0STAT)
Read address
F3h
Write address
73h
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
x
0
After a bus reset
0
x
0
Definition
0
Setup Ready:
This bit is set automatically when a proper setup packet arrives in the 8-byte setup
register, and the EP0RXFIFO is locked. If D0 of INTENBL has been asserted, the
INTR pin is also asserted automatically when this bit is set. The local MCU should
write a “1” in this bit after reading out the 8-byte setup data. When this is performed,
the setup ready bit is reset and the
INTR pin is also deasserted. During a control write,
the packet ready bit of EP0 is reset simultaneously, the lock condition is released, and
it becomes possible to receive packets by EP0 during the data stage. This bit is reset to
“0” by writing a “1” to it. Writing a '0' to this bit will not have any effects on this
register.
Stall bit:
During EP0 reception (in the data stage of a control write transfer), the ML60851E
automatically sets this bit to “1” when a packet with a number of bytes more than the
maximum packet size written in EP0RXPLD is received (or when EOP is missing).
The EP0 can be set to the STALL condition by writing "1" to this bit. When the
following SETUP packet is coming, this bit will be cleared automatically and the EP0
will return from the STALL condition by the procedure based on the USB
specification 2.0. (refer to the USB 2.0 specification)
Bits D7 to D5 and D1 are fixed at “0”, and other values written in them are invalid.
EP0 Stage:
Indicates the stage transition during a control transfer. The transition conditions
between the different stages are shown in the following stage transition diagram.
These bits are automatically set by ML60851E.
Setup Ready (R/Reset)
Stall Bit (R/W)
EP0 Stage (R)
00 = Setup stage
01 = Data stage
10 = Status stage
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