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参数资料
| 型号： | ML60851EGA |
| 厂商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| 封装： | 0.80 MM PITCH, PLASTIC, QFP-44 |
| 文件页数： | 88/88页 |
| 文件大小： | 1137K |
| 代理商： | ML60851EGA |
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Oki Semiconductor
ML60851E
7/84
FUNCTIONS OF REGISTERS
End Point 0 Receive FIFO (EP0RXFIFO)
Read address
40h
Write address
—
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
×
After a bus reset
×
Definition
EP0 Receive data (R)
The receive data from the host computer in the data state during a control Write transfer is stored in EP0RXFIFO.
The EP0 receive data can be read out by the local MCU through reading the address 40h when the ML60851E
issues an EP0 receive packet ready interrupt request. It is possible to read successively the data in the packet by
reading continuously.
The EP0RXFIFO is cleared under the following conditions:
1. When the local MCU resets the EP0 receive packet ready bit (A “1” is written in PKTRDY(0)).
2. When a setup packet is received.
3. When the local MCU writes a “0” in the stall bit (EP0STAT(2)).
End Point 1 Receive FIFO (EP1RXFIFO)
Read address
41h
Write address
—
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
×
After a bus reset
×
Definition
EP1 Receive data (R)
It is possible to read out the EP1 receive data by reading the address 41h. When EP1 is set for bulk reception
(BULK OUT), The local MCU should read EP1RXFIFO when the ML60851E issues an EP1 packet ready
interrupt request. It is possible to read successively the data in the packet by reading continuously. When the data
transfer direction of EP1 is set as “Transmit”, all accesses to this address will be invalid.
The EP1RXFIFO is cleared under the following conditions:
1. When an OUT token is received for EP1.
2. When the EP1 receive packet ready bit is reset. (A “1” is written in PKTRDY(1).)
3. When the local MCU writes a “0” in the stall bit (EP1CON(1)).
Even when a DMA read with a 16-bit width is made from EP1RXFIFO, the address is A7:A0 = 41h.
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