参数资料
型号: ML60851EGA
厂商: OKI ELECTRIC INDUSTRY CO LTD
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP44
封装: 0.80 MM PITCH, PLASTIC, QFP-44
文件页数: 72/88页
文件大小: 1137K
代理商: ML60851EGA
Oki Semiconductor
ML60851E
72/84
DMA (Direct Memory Access)
It is possible to carry out 8-bit wide or 16-bit wide DMA transfer for the bulk transfer of EP1. The data bus used
is the following:
During 8-bit transfer: AD7 to AD0
During 16-bit transfer: D15 toD8, AD7 to AD0
Demand transfer and single transfer are supported. The settings of the DMA transfer mode and parameters are
done using the DMA control register and the DMA interval register described later in this manual.
In the demand transfer mode, the
DREQ pin is asserted when the reading or writing of a data packet becomes
possible. The
DREQ pin is de-asserted when the transfer of all the data of the receive packets is completed by
the external DMA controller. Therefore, other devices cannot access the local bus during DMA transfer.
On the other hand, in the single transfer mode, the
DREQ pin is de-asserted at the end of transfer of the number
of bytes (or words) of one transfer, and the other devices can access the local bus during this period.
Power-down
By setting the system control register (SYSCON) to value A0h, the oscillator circuit of the ML60851E can be
stopped and the ML60851E enters the power-down state.
The ML60851E cannot communicate with the USB bus after the internal oscillations are stopped.
In order to communicate with the USB bus after the termination of the power-down state, the internal oscillations
should be restarted and the initial settings should be done. Therefore, the ML60851E should not be powered
down during normal operation.
Note 1: Assertion of the
RESET signal causes the internal oscillations to be restarted.
Note 2: In the power-down state, reads and writes to the registers are possible but reads or writes to
FIFO are not possible.
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