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参数资料
| 型号： | MPC5561MVZ80R |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | MICROCONTROLLER, PBGA324 |
| 封装： | 23 X 23 MM, 1 MM PITCH, MS-034AAJ-1, LEAD FREE, TEPBGA-324 |
| 文件页数： | 46/56页 |
| 文件大小： | 1044K |
| 代理商： | MPC5561MVZ80R |
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MPC5561 Microcontroller Data Sheet, Rev. 2.0
Revision History for the MPC5561 Data Sheet
Freescale Semiconductor
50
Table 7 Power Sequence Pin Status for Fast Pads
Changed title to Pin Status for Fast Pads During the Power Sequence
Changed preceding paragraph
From: Although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive
current spikes, etc., the state of the I/O pins during power up/down varies depending on power. Prior to exiting
POR, the pads are in a high impedance state (Hi-Z).
To: There are no power up/down sequencing requirements to prevent issues such as latch-up, excessive current
spikes, and so on. Therefore, the state of the I/O pins during power up/down varies depending on which supplies
are powered.
Deleted the ‘Comment’ column.
Added a POR column after the VDD column.
Added row 2:’ VDDE, Low, Low, Asserted, High’ and row 5: VDDE, VDD33, VDD, Asserted, Hi-Z.
Table 8 Power Sequence Pin Status for Medium/Slow Pads:
Changed title to Pin Status for Medium and Slow Pads During the Power Sequence
Updated preceding paragraph.
Deleted the ‘Comment’ column.
Added a POR column after the VDD column.
Added row 3:’ VDDEH, VDD, Asserted, Hi-Z.’
Table 9 DC Electrical Specifications:
Spelled out meaning of the slash ‘/’ as ‘and’ as well as ‘I/O’ as ‘input/output.’ Sentence still very confusing.
Deleted ‘input/output’ from the specs to improve clarity.
Spec 20, column 2, Characteristics,’ Slow and medium output high voltage (IOH_S = –2.0 mA):’
Created a left-justified second line and moved ‘IOH_S = –2.0 mA’ from the 1st line to the second line and deleted
the parentheses. Created a left-justified third line that reads ‘IOH_S = –1.0 mA.’
Spec 20, column 4, Min.: Added a blank line before and after ‘0.80
× V
DDEH’ and put ‘0.85 × VDDEH’ on the last
line.
Spec 22, column 2,’Slow and medium output low voltage (IOL_S = 2.0 mA):’ Created a left-justified second line
and moved ‘IOL_S = 2.0 mA.’ from the 1st line to the second line and deleted the parentheses. Created a
left-justified third line that reads ‘IOL_S = 1.0 mA.’
Spec 22, column 5, Max.: Added a blank line before and after ‘0.20
× V
DDEH’ and put ‘0.15 × VDDEH’ on the last
line.
Spec 26: Changed ‘AN[12]_MA[1]_SDO’ to ‘AN[13]_MA[1]_SDO’.
Spec 27a: Changed 132 MHz to 135 MHz. Added maximum values for 8-way cache:
1.65 typical = 630
1.35 typical = 500
1.65 high = 785
1.35 high = 630
All 8-way cache max values have footnote 11.
Added 4-way cache with footnote 10:
1.65 high = 685 with footnote 11
1.35 high = TBD with footnote 12
Spec 27b, Operating current 1.5 V supplies @ 114 MHz: Added maximum values for 8-way cache:
1.65 typical = 600,
1.35 typical = 450,
1.65 high = 680,
1.35 high = 500.
All 8-way cache max values have footnote 11.
Added 4-way cache with footnote 10:
1.65 and 1.35 high = TBD with footnote 12
Table 28. Table and Figure Changes Between Rev. 0.0 and 1.0 (continued)
Location
Description of Changes
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