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参数资料
| 型号： | MPC5561MVZ80R |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | MICROCONTROLLER, PBGA324 |
| 封装： | 23 X 23 MM, 1 MM PITCH, MS-034AAJ-1, LEAD FREE, TEPBGA-324 |
| 文件页数： | 47/56页 |
| 文件大小： | 1044K |
| 代理商： | MPC5561MVZ80R |
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Revision History for the MPC5561 Data Sheet
MPC5561 Microcontroller Data Sheet, Rev. 2.0
Freescale Semiconductor
51
Table 9 DC Electrical Specifications: (continued)
Spec 27c, Operating current 1.5 V supplies @ 82 MHz: Added maximum values for 8-way cache:
1.65 typical = 490,
1.35 typical = 360,
1.65 high = 520,
1.35 high = 390.
All 8-way cache max values have footnote 11.
Added 4-way cache values
1.65 high = TBD and 1.35 high = TBD, both with footnote 12.
Spec 28: Changed 132 MHz to 135 MHz.
Spec 29: Deleted frequency information.
Corrected footnote 3 to read: If standby operation is not required, connect the VSTBY to ground.
Combined old footnotes 11 and 12 for new footnote 6 and added to specs 27a, b, and c on the 8-way cache line
that reads: Eight-way cache enabled (L1CSR0[CORG] = 0b0).
Added footnote 10 to specs 27a, b, and c on the 4-way cache line that reads: Four-way cache enabled
(L1CSR0[CORG] = 0b1) or (L1CSR0[CORG] = 0b0 with L1CSR0[WAM] = 0b1, L1CSR0[WID] = 0b1111,
L1CSR0[WDD] = 0b1111, L1CSR0[AWID] = 0b1, and L1CSR0[AWDD] = 0b1).
Added footnote 11 to specs 27a, b, and c on the max numeric values: “Preliminary. Specification pending final
characterization.”
Added footnote 12 to specs 27a, b, and c on the max TBD values: “Specification pending final characterization.”
Table 12 FMPLL Electrical Characteristics:
Added (TA = TL – TH) to the second line of the table title.
Spec 1, footnote 1 in column 2: ‘PLL reference frequency range.’: Changed to read ‘Nominal crystal and external
reference values are worst-case not more than 1%. The device operates correctly if the frequency remains within
± 5% of the specification limit. This tolerance range allows for a slight frequency drift of the crystals over time.
The designer must thoroughly understand the drift margin of the source clock.‘
Spec 1, added two more lines to the PLL reference frequency range’ to read as follows
:
crystal reference (20)
fref_crystal
8
≤ 20
crystal reference (40)
fref_crystal
> 20
40
external reference (20)
fref_ext
8
≤ 20
external reference (40)
fref_ext
> 20
40
Spec 1, footnote 2 in column 2: ‘PLL reference frequency range.’: Changed to: ‘The 8–20 MHz crystal or external
reference values have PLLCFG[2] pulled low’ and applies to spec 1, column 2, crystal reference and external
reference.
Spec 1, footnote 2 in column 2: ‘PLL reference frequency range,’ Changed to: The 20–40 MHz crystal and
external reference values have PLLCFG[2] pulled high, and the minimum frequency must be greater than 20
MHz. Use the 8–20 MHz setting (PLLCFG[2] pulled low) if a 20 MHz crystal or external reference is required. To
exit RESET when using 40 MHz, set PLLCFG[2] to 1.
Specs 12 and 13: Grouped (2 x Cl).
Spec 21, column 2: Changed fref_crystal to fref in ICO frequency equation, and
added the same equation but substituted fref_ext for fref for the external reference clock, giving:
fico = [ fref_crystal × (MFD + 4) ] ÷ (PREDIV + 1)
fico = [ fref_ext × (MFD + 4) ] ÷ (PREDIV + 1)
Spec 21, column 4, Max.: Deleted old footnote 18 that reads:
The ICO frequency can be higher than the maximum allowable system frequency. For this case, set the CMPLL
synthesizer control register reduced frequency divider (FMPLL_SYNCR[RFD]) to divide-by-two (RFD = 0b001).
Therefore, for a 40 MHz maximum device (system frequency), program the FMPLL to generate 80 MHz at the
ICO output and then divide-by-two the RFD to provide the 40 MHz system clock.’
Spec 21: Changed column 5 from ‘82 or 66 MHz’ to: ‘150’.
Spec 22: Changed column 4, Max. Value from fMAX to 20, and added footnote 20 to read, ‘Maximum value for
dual controller (1:1) mode is (fMAX ÷ 2) and the predivider set to 1 (FMPLL_SYNCR[PREDIV] = 0b001).’
Table 28. Table and Figure Changes Between Rev. 0.0 and 1.0 (continued)
Location
Description of Changes
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