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参数资料
| 型号： | MPC5561MVZ80R |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | MICROCONTROLLER, PBGA324 |
| 封装： | 23 X 23 MM, 1 MM PITCH, MS-034AAJ-1, LEAD FREE, TEPBGA-324 |
| 文件页数： | 50/56页 |
| 文件大小： | 1044K |
| 代理商： | MPC5561MVZ80R |
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MPC5561 Microcontroller Data Sheet, Rev. 2.0
Revision History for the MPC5561 Data Sheet
Freescale Semiconductor
54
Table 9 DC Electrical Specifications
Added footnote that reads: VDDE2 and VDDE3 are limited to 2.25–3.6 V only if EBTS = 0; VDDE2 and VDDE3 have
a range of 1.6–3.6 V if EBTS =1.
Spec 27a, Operating current 1.5 V supplies @ 135 MHz:
-- 8-way 1.65 V typical use: from 630 to 620
-- 8-way 1.35 V typical use: from 500 to 440
-- 8-way 1.65 V high use: from 785 to 670
-- 8-way 1.35 V high use: from 630 to 490
-- 4-way 1.65 V high use: from 710 to 620
-- 4-way 1.35 V high use: from 550 to 430
Spec 27b, Operating current 1.5 V supplies @ 114 MHz:
-- 8-way 1.65 V typical use: from 600 to 590
-- 8-way 1.35 V typical use: from 450 to 395
-- 8-way 1.65 V high use: from 680 to 580
-- 8-way 1.35 V high use: from 500 to 390
-- 4-way 1.65 V high use: from 650 to 550
-- 4-way 1.35 V high use: from 490 to 385
Spec 27c, Operating current 1.5 V supplies @ 82 MHz:
-- 8-way 1.65 V typical use: from 490 to 485
-- 8-way 1.35 V typical use: from 360 to 320
-- 8-way 1.65 V high use: from 545 to 470
-- 8-way 1.35 V high use: from 400 to 315
-- 4-way 1.65 V high use: from 530 to 460
-- 4-way 1.35 V high use: from 395 to 310
Removed footnote 12 on all these changed values: Preliminary. Specification pending final characterization.
Table 17 Pad AC Specifications
Footnote 1, changed ‘VDDEH = 4.5–5.5;’ to ‘VDDEH = 4.5–5.25;’
Footnote 1, deleted ‘fSYS = 132 MHz.’
Footnote 2, changed from ‘tested’ to ‘(not tested).’
Footnote 3, changed from ‘Out delay. . .’ to ‘The output delay. . .’,
Changed from ‘Add a maximum of one system clock to the output delay to get the output delay with respect to
the system clock‘ to ‘To calculate the output delay with respect to the system clock, add a maximum of one system
clock to the output delay.’
Footnote 4: changed ‘Delay’ to ‘The output delay.’
Footnote 5: deleted ‘before qualification.’
Changed from ‘This parameter is supplied for reference and is not guaranteed by design and not tested’ to ‘This
parameter is supplied for reference and is guaranteed by design and tested.’
Table 22 Bus Operation Timing:
External Bus Frequency in the table heading: Added footnote that reads: Speed is the nominal maximum
frequency. Max. speed is the maximum speed allowed including frequency modulation (FM). 82 MHz parts allow
for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM, and 135 MHz parts
allow for 132 MHz system clock + 2% FM.
Spec 1: Changed the values in Min. columns: 40 MHz from 25 to 24.4; 56 MHz from 17.9 to 17.5
Specs 7 and 8: Removed from external bus interface: BDIP, OE, TSIZ[0:1], and WE/BE[0:3].
Added a footnote each for the DATA[0:31], TEA, and WE/BE[0:3] signals in the table: Due to pin limitations, the
DATA[16:31], TEA, and WE/BE[2:3] signals are not available on the 324 package.
Table 29. Information Changed Between Rev. 1.0 and Rev. 2.0 (continued)
Location
Description of Changes
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