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| 型号： | MPC8313E-RDBB |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 95/99页 |
| 文件大小： | 0K |
| 描述： | BOARD CPU 8313E VER 2.1 |
| 标准包装： | 1 |
| 系列： | PowerQUICC II™ PRO |
| 类型： | MPU |
| 适用于相关产品： | MPC8313E |
| 所含物品： | 板 |
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MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
95
24 Revision History
This table summarizes a revision history for this document.
Table 73. Document Revision History
Rev.
Number
Date
Substantive Change(s)
4
11/2011
In Table 2, added following notes:
–
Note 3: Min temperature is specified with TA; Max temperature is specified with TJ
–
Note 4: All Power rails must be connected and power applied to the MPC8313 even if the IP
interfaces are not used.
–
Note 5: All I/O pins should be interfaced with peripherals operating at same voltage level.
–
Note 6: This voltage is the input to the filter discussed in Section 22.2, “PLL Power Supply Filtering.”
and not necessarily the voltage at the AVDD pin, which may be reduced from VDD by the filter
Decoupled PCI_CLK and SYS_CLK_IN rise and fall times in Table 8. Relaxed maximum rise/fall time
of SYS_CLK_IN to 4ns.
Added a note in Table 27 stating “The frequency of RX_CLK should not exceed the TX_CLK by more
than 300 ppm."
In Table 30:
–
Changed max value of tskrgt in “Data to clock input skew (at receiver)” row from 2.8 to 2.6.
–
Added Note 7, stating that, “The frequency of RX_CLK should not exceed the GTX_CLK125 by
more than 300 ppm.”
Added a note stating “eTSEC should be interfaced with peripheral operating at same voltage level” in
TSEC1_MDC and TSEC_MDIO are powered at 3.3V by NVDD. Replaced LVDDA/LVDDB with NVDD
and removed instances of 2.5V at several places in Section 8.5, “Ethernet Management Interface
In Table 62:
–
Added Note 2 for LGPL4 in showing LGPL4 as open-drain.
–
Removed Note 2 from TSEC1_MDIO.
–
Added Note 10: This pin has an internal pull-up.
–
Added Note 11: This pin has an internal pull-down.
–
Added Note 12: “In MII mode, GTX_CLK should be pulled down by 300
to V
SS” to
TSEC1_GTX_CLK and TSEC2_GTX_CLK.
In Section 19.1, “Package Parameters for the MPC8313E TEPBGAII,” replaced "5.5 Sn/0.5 Cu/4 Ag"
with "Sn/3.5 Ag."
Added foot note 3 in Table 65 stating “The VCO divider needs to be set properly so that the System
PLL VCO frequency is in the range of 450–750 MHz.”
In Table 72:
–
Added AD = 266 and D = 266.
–
Added “C = 2.2” in “Revision level” column.
–
Added Note 4.
Changed resitor from 1.0
to 10 in Figure 58.
Replaced LCCR with LCRR throughout.
Added high-speed to USB Phy description.
3
01/2009
Table 72, in column aa, changed to AG = 400 MHz.
2.2
12/2008
Made cross-references active for sections, figures, and tables.
2.1
12/2008
Added Figure 2, after Table 2 and renumbered the following figures.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC8313E-RDBB | 制造商:Freescale Semiconductor 功能描述:; LEADED PROCESS COMPATIBLE:YES; PEAK RE |
| MPC8313E-RDBC | 功能描述:开发板和工具包 - 其他处理器 8313E CPU board Ver 2.2 RoHS:否 制造商:Freescale Semiconductor 产品:Development Systems 工具用于评估:P3041 核心:e500mc 接口类型:I2C, SPI, USB 工作电源电压: |
| MPC8313EVRADD | 制造商:Freescale Semiconductor 功能描述:MPC83XX RISC 32-BIT 90NM 333MHZ 1V/1.8V/2.5V/3.3V 516-PIN TE - Trays |
| MPC8313EVRADDB | 功能描述:微处理器 - MPU PBGA W/ ENCR RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8313EVRADDC | 功能描述:微处理器 - MPU 8313 REV2.2 W/ENC RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
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