参数资料
型号: MPC8541ECPXAKF
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 600 MHz, RISC PROCESSOR, PBGA783
封装: 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783
文件页数: 46/88页
文件大小: 1221K
代理商: MPC8541ECPXAKF
MPC8541E PowerQUICC III Integrated Communications Processor Hardware Specification, Rev. 3.2
50
Freescale Semiconductor
I2C
12.2
I2C AC Electrical Specifications
Table 40 provides the AC timing parameters for the I2C interface of the MPC8541E.
Capacitance for each I/O pin
CI
—10
pF
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. CB = capacitance of one bus line in pF.
3. Refer to the MPC8555E PowerQUICC III Integrated Communications Processor Reference Manual for information on the
digital filter used.
4. I/O pins will obstruct the SDA and SCL lines if OVDD is switched off.
Table 40. I2C AC Electrical Specifications
All values refer to VIH (min) and VIL (max) levels (see Table 39).
Parameter
Symbol 1
Min
Max
Unit
SCL clock frequency
fI2C
0
400
kHz
Low period of the SCL clock
tI2CL
6
1.3
μs
High period of the SCL clock
tI2CH
6
0.6
μs
Setup time for a repeated START condition
tI2SVKH
6
0.6
μs
Hold time (repeated) START condition (after this period, the first clock
pulse is generated)
tI2SXKL
6
0.6
μs
Data setup time
tI2DVKH
6
100
ns
Data hold time:
CBUS compatible masters
I2C bus devices
tI2DXKL
0 2
0.9 3
μs
Rise time of both SDA and SCL signals
tI2CR
20 + 0.1 Cb
4
300
ns
Fall time of both SDA and SCL signals
tI2CF
20 + 0.1 Cb
4
300
ns
Set-up time for STOP condition
tI2PVKH
0.6
μs
Bus free time between a STOP and START condition
tI2KHDX
1.3
μs
Noise margin at the LOW level for each connected device (including
hysteresis)
VNL
0.1
× OV
DD
—V
Table 39. I2C DC Electrical Characteristics
At recommended operating conditions with OVDD of 3.3 V ± 5%.
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