- 您现在的位置：买卖IC网 > PDF目录183323 > MPC93H52FAR2 (INTEGRATED DEVICE TECHNOLOGY INC) PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 PDF资料下载
参数资料
| 型号： | MPC93H52FAR2 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | LQFP-32 |
| 文件页数： | 12/16页 |
| 文件大小： | 285K |
| 代理商： | MPC93H52FAR2 |
MPC93H52
MOTOROLA
3.3V 1:11 LVCMOS Zero Delay Clock Generator
5
Table 6. AC CHARACTERISTICS (VCC = 3.3 V ± 5%, TA = 0° to 70°C)a
a. AC characteristics apply for parallel output termination of 50
to V
TT
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input reference frequency
÷4 feedback
in PLL modeb c
÷6 feedback
÷8 feedback
÷12 feedback
Input reference frequency in PLL bypass moded
b. PLL mode requires PLL_EN=0 to enable the PLL and zero-delay operation.
c. The PLL may be unstable with a divide by 2 feedback ratio.
d. In PLL bypass mode, the MPC93H52 divides the input reference clock.
50.0
33.3
25.0
16.67
50.0
120.0
80.0
60.0
40.0
250.0
MHz
fVCO
VCO lock frequency rangee
e. The input frequency f
ref on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: fref = fVCO ÷ FB.
200
480
MHz
fMAX
Output Frequency
÷2 outputf
÷4 output
÷6 output
÷8 output
÷12 output
f.
See Table 7 and Table 8 for output divider configurations.
100
50
33.3
25
16.67
240
120
80
60
40
MHz
tPWMIN Minimum Reference Input Pulse Width
2.0
ns
tr, tf
CCLK Input Rise/Fall Timeg
g. The MPC93H52 will operate with input rise and fall times up to 3.0 ns, but the AC characteristics, specifically t
(
), can only be guaranteed if tr/tf
are within the specified range.
1.0
ns
0.8 to 2.0V
t()
Propagation Delay CCLK to FB_IN
(fref = 50MHz)
(static phase offset)
–200
+200
ps
PLL locked
tsk(O)
Output-to-output Skewh
all outputs, any frequency
within QA output bank
within QB output bank
within QC output bank
h. See application section for part-to-part skew calculation.
300
200
100
ps
DC
Output duty cycle
45
50
55
%
tr, tf
Output Rise/Fall Time
0.1
1.0
ns
0.55 to 2.4V
tPLZ, HZ Output Disable Time
8
ns
tPZL, LZ Output Enable Time
10
ns
tJIT(CC) Cycle-to-cycle jitter
output frequencies mixed
all outputs same frequency
150
25
ps
RMS
tJIT(PER) Period Jitter
output frequencies mixed
all outputs same frequency
75
20
ps
RMS
tJIT() I/O Phase Jitteri
÷4 feedback divider RMS (1 σ)
÷6 feedback divider RMS (1 σ)
÷8 feedback divider RMS (1 σ)
÷12 feedback divider RMS (1 σ)
i.
See application section for a jitter calculation for other confidence factors than 1
σ.
40
ps
BW
PLL closed loop bandwidthj
÷4 feedback
÷6 feedback
÷8 feedback
÷12 feedback
j.
–3 dB point of PLL transfer characteristics.
2.0-8.0
1.0-4.0
0.8-2.5
0.6-1.5
MHz
tLOCK Maximum PLL Lock Time
10
ms
相关PDF资料 |
PDF描述 |
|---|---|
| MPC946FAR2 | 946 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| mPD789322 | 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash |
| mPD789327GB-xxx-8ET | 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash |
| MPDTH03060WAH | 1-OUTPUT 25 W DC-DC REG PWR SUPPLY MODULE |
| MPLC0525L2R2 | 1 ELEMENT, 2.2 uH, GENERAL PURPOSE INDUCTOR, SMD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC93R51 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC93R51AC | 功能描述:时钟驱动器及分配 3.3V 240MHz Clock Generator RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| MPC93R51ACR2 | 功能描述:时钟发生器及支持产品 FSL 1-9 LVCMOS/LVPEC L to LVCMOS PLL Cloc RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC93R51D | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC93R51FA | 功能描述:时钟驱动器及分配 3.3V 240MHz Clock Generator RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
发布紧急采购，3分钟左右您将得到回复。