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参数资料
| 型号： | MPC93H52FAR2 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | LQFP-32 |
| 文件页数： | 15/16页 |
| 文件大小： | 285K |
| 代理商： | MPC93H52FAR2 |
MPC93H52
8
3.3V 1:11 LVCMOS Zero Delay Clock Generator
MOTOROLA
Power Supply Filtering
The MPC93H52 is a mixed analog/digital product. Its
analog circuitry is naturally susceptible to random noise,
especially if this noise is seen on the power supply pins.
Random noise on the VCCA (PLL) power supply impacts
the device characteristics, for instance I/O jitter. The
MPC93H52 provides separate power supplies for the
output buffers (VCC) and the phase-locked loop (VCCA) of
the device. The purpose of this design technique is to iso-
late the high switching noise digital outputs from the rela-
tively sensitive internal analog phase-locked loop. In a
digital system environment where it is more difficult to
minimize noise on the power supplies a second level of
isolation may be required. The simple but effective form
of isolation is a power supply filter on the VCCA pin for the
MPC93H52. Figure 7 illustrates a typical power supply fil-
ter scheme. The MPC93H52 frequency and phase stabil-
ity is most susceptible to noise with spectral content in
the 100kHz to 20MHz range. Therefore the filter should
be designed to target this range. The key parameter that
needs to be met in the final filter design is the DC voltage
drop across the series filter resistor RF. From the data
sheet the ICCA current (the current sourced through the
VCCA pin) is typically 8 mA (12 mA maximum), assuming
that a minimum of 2.98V must be maintained on the VCCA
pin. The resistor RF shown in Figure 7 “VCCA Power Sup-
ply Filter” should have a resistance of 5-25
to meet the
voltage drop criteria.
Figure 7. VCCA Power Supply Filter
The minimum values for RF and the filter capacitor CF
are defined by the required filter characteristics: the RC
filter should provide an attenuation greater than 40 dB for
noise whose spectral content is above 100 kHz. In the ex-
ample RC filter shown in Figure 7 “VCCA Power Supply
Filter”, the filter cut-off frequency is around 3-5 kHz and
the noise attenuation at 100 kHz is better than 42 dB.
As the noise frequency crosses the series resonant
point of an individual capacitor its overall impedance
begins to look inductive and thus increases with
increasing frequency. The parallel capacitor combination
shown ensures that a low impedance path to ground
exists for frequencies well above the bandwidth of the
PLL. Although the MPC93H52 has several design
features to minimize the susceptibility to power supply
noise (isolated power and grounds and fully differential
PLL) there still may be applications in which overall
performance is being degraded due to system power
supply noise. The power supply filter schemes discussed
in this section should be adequate to eliminate power
supply noise related problems in most designs.
Using the MPC93H52 in zero-delay applications
Nested clock trees are typical applications for the
MPC93H52. Designs using the MPC93H52 as LVCMOS
PLL fanout buffer with zero insertion delay will show sig-
nificantly lower clock skew than clock distributions devel-
oped from CMOS fanout buffers. The external feedback
option of the MPC93H52 clock driver allows for its use as
a zero delay buffer. One example configuration is to use
a
÷4 output as a feedback to the PLL and configuring all
other outputs to a divide-by-4 mode. The propagation de-
lay through the device is virtually eliminated. The PLL
aligns the feedback clock output edge with the clock input
reference edge resulting a near zero delay through the
device. The maximum insertion delay of the device in ze-
ro-delay applications is measured between the reference
clock input and any output. This effective delay consists
of the static phase offset, I/O jitter (phase or long-term jit-
ter), feedback path delay and the output-to-output skew
error relative to the feedback output.
Calculation of part-to-part skew
The MPC93H52 zero delay buffer supports applica-
tions where critical clock signal timing can be maintained
across several devices. If the reference clock inputs of
two or more MPC93H52 are connected together, the
maximum overall timing uncertainty from the common
CCLK input to any output is:
tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF
This maximum timing uncertainty consist of 4 compo-
nents: static phase offset, output skew, feedback board
trace delay and I/O (phase) jitter:
Figure 8. MPC93H51 maximum device-to-device skew
VCCA
VCC
MPC93H52
10 nF
CF
RF
VCC
33...100 nF
RF = 5–25
CF = 22 mF
tPD,LINE(FB)
tJIT()
+tSK(O)
—t()
+t()
tJIT()
+tSK(O)
tSK(PP)
Max. skew
CCLKCommon
QFBDevice 1
Any QDevice 1
QFBDevice2
Any QDevice 2
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| MPC93R51ACR2 | 功能描述:时钟发生器及支持产品 FSL 1-9 LVCMOS/LVPEC L to LVCMOS PLL Cloc RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC93R51D | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC93R51FA | 功能描述:时钟驱动器及分配 3.3V 240MHz Clock Generator RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
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