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参数资料
| 型号： | MPC93H52FAR2 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | LQFP-32 |
| 文件页数： | 13/16页 |
| 文件大小： | 285K |
| 代理商： | MPC93H52FAR2 |
MPC93H52
6
3.3V 1:11 LVCMOS Zero Delay Clock Generator
MOTOROLA
APPLICATIONS INFORMATION
Programming the MPC93H52
The MPC93H52 supports output clock frequencies
from 16.67 to 240 MHz. Different feedback and output
divider configurations can be used to achieve the desired
input to output frequency relationship. The feedback
frequency and divider should be used to situate the VCO
in the frequency lock range between 200 and 480 MHz
for stable and optimal operation. The FSELA, FSELB,
FSELC pins select the desired output clock frequencies.
Possible frequency ratios of the reference clock input to
the outputs are 1:1, 1:2, 1:3, 3:2 as well as 2:3, 3:1 and
2:1. Table 1 illustrates the various output configurations
and frequency ratios supported by the MPC93H52. See
also Table 7, Table 8 and Figure 3 to Figure 6 for further
reference. A ÷2 output divider cannot be used for
feedback.
Figure 1
Figure 2
Table 7. MPC93H52 Example Configuration (F_RANGE = 0)
PLL
Feedback
frefa
[MHz]
a. fref is the input clock reference frequency (CCLK)
FSELA FSELB FSELC
QA[0:4]:fref ratio
QB[0:3]:fref ratio
QC[0:1]:fref ratio
VCO
÷ 4b
b. fref is the input clock reference frequency (CCLK)
50-120
0
fref
(50-120 MHz) fref
2
(100-240 MHz)
0
1
fref
(50-120 MHz) fref
(50-120 MHz)
1
0
fref
2÷3
(33-80 MHz) fref
(50-120 MHz) fref
2
(100-240 MHz)
1
0
1
fref
2÷3
(33-80 MHz) fref
(50-120 MHz) fref
(50-120 MHz)
VCO
÷ 6c
c. fref is the input clock reference frequency (CCLK)
33.3-80
1
0
fref
(33-80 MHz) fref
3÷2 (50-120 MHz) fref 3
(100-240 MHz)
1
0
1
fref
(33-80 MHz) fref
3÷2 (50-120 MHz) fref 3÷2 (50-120 MHz)
1
0
fref
(33-80 MHz) fref
3
(100-240 MHz) fref
3
(100-240 MHz)
1
fref
(33-80 MHz) fref
3
(100-240 MHz) fref
3÷2 (50-120 MHz)
Table 8. MPC93H52 Example Configurations (F_RANGE = 1)
PLL
Feedback
frefa
[MHz]
FSELA FSELB FSELC
QA[0:4]:fref ratio
QB[0:3]:fref ratio
QC[0:1]:fref ratio
VCO
÷ 8b
25-60
000
fref
(25-60 MHz) fref
2
(50-120 MHz)
001
fref
(25-60 MHz) fref
(25-60 MHz)
100
fref
2÷3
(16-40 MHz) fref
(25-60 MHz) fref
2
(50-120 MHz)
101
fref
2÷3
(16-40 MHz) fref
(25-60 MHz) fref
(25-60 MHz)
VCO
÷ 12c
16.67-40
1
0
fref
(16-40 MHz) fref
3÷2
(25-60 MHz) fref
3
(50-120 MHz)
101
fref
(16-40 MHz) fref
3÷2
(25-60 MHz) fref
3÷2
(25-60 MHz)
110
fref
(16-40 MHz) fref
3
(50-120 MHz) fref
3
(50-120 MHz)
111
fref
(16-40 MHz) fref
3
(50-120 MHz) fref
3÷2
(25-60 MHz)
a. fref is the input clock reference frequency (CCLK)
b. QAx connected to FB_IN and FSELA=0
c. QAx connected to FB_IN and FSELA=1
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