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参数资料
| 型号： | MPC93H52FAR2 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | LQFP-32 |
| 文件页数： | 14/16页 |
| 文件大小： | 285K |
| 代理商： | MPC93H52FAR2 |
MPC93H52
MOTOROLA
3.3V 1:11 LVCMOS Zero Delay Clock Generator
7
Example Configurations for the MPC93H52
Figure 3. MPC93H52 Default Configuration
Figure 4. MPC93H52 Zero Delay Buffer Configuration
Figure 5. .MPC93H52 Default Configuration
Figure 6. MPC93H52 Zero Delay Buffer Configuration 2
F_RANGE
MPC93H52
fref = 100 MHz
100 MHz
100 MHz (Feedback)
200 MHz
CCLK
FB_IN
FSELA
FSELB
FSELD
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC0
QC1
QA4
MPC93H52 default configuration (feedback of QB0 = 100
MHz). All control pins are left open.
Frequency range
Min
Max
Input
50 MHz
120 MHz
QA outputs
50 MHz
120 MHz
QB outputs
50 MHz
120 MHz
QC outputs
100 MHz
240 MHz
F_RANGE
MPC93H52
fref = 62.5 MHz
62.5 MHz
62.5 MHz (Feedback)
62.5 MHz
MPC93H52 zero-delay (feedback of QB0 = 62.5 MHz). All
control pins are left open except FSELC = 1. All outputs are
locked in frequency and phase to the input clock.
CCLK
FB_IN
FSELA
FSELB
FSELC
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC0
QC1
QA4
VCC
Frequency range
Min
Max
Input
50 MHz
120 MHz
QA outputs
50 MHz
120 MHz
QB outputs
50 MHz
120 MHz
QC outputs
50 MHz
120 MHz
F_RANGE
Frequency range
Min
Max
Input
25 MHz
60 MHz
QA outputs
50 MHz
120 MHz
QB outputs
50 MHz
120 MHz
QC outputs
100 MHz
240 MHz
MPC93H52
fref = 33.3 MHz
33.3 MHz
50 MHz
33.3 MHz (Feedback)
100 MHz
MPC93H52 configuration to multiply the reference frequen-
cy by 3, 32 and 1. PLL feedback of QA4 = 33.3 MHz.
CCLK
FB_IN
FSELA
FSELB
FSELC
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC0
QC1
QA4
VCC
F_RANGE
Frequency range
Min
Max
Input
25 MHz
60 MHz
QA outputs
25 MHz
60 MHz
QB outputs
25 MHz
60 MHz
QC outputs
25 MHz
60 MHz
MPC93H52
fref = 33.3 MHz
33.3 MHz
33.3 MHz (Feedback)
33.3 MHz
MPC93H52 zero-delay (feedback of QB0 = 33.3 MHz).
Equivalent to Table 2 except F_RANGE = 1 enabling a
lower input and output clock frequency.
CCLK
FB_IN
FSELA
FSELB
FSELC
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC0
QC1
QA4
VCC
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