- 您现在的位置：买卖IC网 > PDF目录183323 > MPC93H52FAR2 (INTEGRATED DEVICE TECHNOLOGY INC) PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 PDF资料下载
参数资料
| 型号： | MPC93H52FAR2 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | LQFP-32 |
| 文件页数： | 16/16页 |
| 文件大小： | 285K |
| 代理商： | MPC93H52FAR2 |
MPC93H52
MOTOROLA
3.3V 1:11 LVCMOS Zero Delay Clock Generator
9
Due to the statistical nature of I/O jitter a RMS value
(1
σ) is specified. I/O jitter numbers for other confidence
factors (CF) can be derived from Table 9.
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation
a I/O jitter confidence factor of 99.7% (
± 3σ) is assumed,
resulting in a worst case timing uncertainty from input to
any output of -445 ps to 395 ps relative to CCLK:
tSK(PP) = [–200ps...150ps] + [–200ps...200ps] +
[(15ps –3)...(15ps 3)] + tPD, LINE(FB)
tSK(PP) = [–445ps...395ps] + tPD, LINE(FB)
Driving Transmission Lines
The MPC93H52 clock driver was designed to drive
high speed signals in a terminated transmission line en-
vironment. To provide the optimum flexibility to the user
the output drivers were designed to exhibit the lowest im-
pedance possible. With an output impedance of less than
20
the drivers can drive either parallel or series termi-
nated transmission lines. For more information on trans-
mission lines the reader is referred to Motorola
application note AN1091. In most high performance clock
networks point-to-point distribution of signals is the meth-
od of choice. In a point-to-point scheme either series ter-
minated or parallel terminated transmission lines can be
used. The parallel technique terminates the signal at the
end of the line with a 50
resistance to VCC÷2.
This technique draws a fairly high level of DC current
and thus only a single terminated line can be driven by
each output of the MPC93H52 clock driver. For the series
terminated case however there is no DC current draw,
thus the outputs can drive multiple series terminated
lines. Figure 9. Single versus Dual Transmission Lines
illustrates an output driving a single series terminated line
versus two series terminated lines in parallel. When tak-
en to its extreme the fanout of the MPC93H52 clock driv-
er is effectively doubled due to its capability to drive
multiple lines.
The waveform plots in Figure 10. Single versus Dual
Waveforms and Figure 11. Optimized Dual Line Termina-
tion show the simulation results of an output driving a
Figure 9. Single versus Dual Transmission Lines
single line versus two lines. In both cases the drive capa-
bility of the MPC93H51 output buffer is more than suffi-
cient to drive 50
transmission lines on the incident
edge. Note from the delay measurements in the simula-
tions a delta of only 43ps exists between the two differ-
ently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output-to-output skew of the MPC93H51. The output
waveform in Figure 10. Single versus Dual Waveforms
and Figure 11. Optimized Dual Line Termination shows a
step in the waveform, this step is caused by the imped-
ance mismatch seen looking into the driver. The parallel
combination of the 36
series resistor plus the output
impedance does not match the parallel combination of
the line impedances. The voltage wave launched down
the two lines will equal:
VL = VS ( Z0 ÷ (RS+R0 +Z0))
Z0 = 50 || 50
RS = 40 || 40
R0 = 10
VL = 3.0 ( 25 ÷ (20+10+25)
= 1.36V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.7V. It will then increment
towards the quiescent 3.0V in steps separated by one
round trip delay (in this case 4.0ns).
Since this step is well above the threshold region it will
not cause any false clock triggering, however designers
may be uncomfortable with unwanted reflections on the
line. To better match the impedances when driving multi-
ple lines the situation in Figure 11. Optimized Dual Line
Termination should be used. In this case the series termi-
nating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the
line impedance is perfectly matched.
Table 9. Confidence Facter CF
CF
Probability of clock edge within the distribution
± 1σ
0.68268948
± 2σ
0.95449988
± 3σ
0.99730007
± 4σ
0.99993663
± 5σ
0.99999943
± 6σ
0.99999999
10
IN
MPC93H52
OUTPUT
BUFFER
RS =40
ZO = 50
OutA
10
IN
MPC93H52
OUTPUT
BUFFER
RS =40
ZO = 50
OutB0
RS = 40
ZO = 50
OutB1
相关PDF资料 |
PDF描述 |
|---|---|
| MPC946FAR2 | 946 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| mPD789322 | 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash |
| mPD789327GB-xxx-8ET | 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash |
| MPDTH03060WAH | 1-OUTPUT 25 W DC-DC REG PWR SUPPLY MODULE |
| MPLC0525L2R2 | 1 ELEMENT, 2.2 uH, GENERAL PURPOSE INDUCTOR, SMD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC93R51 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC93R51AC | 功能描述:时钟驱动器及分配 3.3V 240MHz Clock Generator RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| MPC93R51ACR2 | 功能描述:时钟发生器及支持产品 FSL 1-9 LVCMOS/LVPEC L to LVCMOS PLL Cloc RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC93R51D | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC93R51FA | 功能描述:时钟驱动器及分配 3.3V 240MHz Clock Generator RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
发布紧急采购，3分钟左右您将得到回复。