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参数资料
| 型号： | MPC93H52FAR2 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | LQFP-32 |
| 文件页数： | 3/16页 |
| 文件大小： | 285K |
| 代理商： | MPC93H52FAR2 |
MPC93H52
MOTOROLA
3.3V 1:11 LVCMOS Zero Delay Clock Generator
11
Figure 13. Output to output Skew tSK(O)
Figure 14. .Propagation delay (t(), status phase offset)
test reference
Figure 15. Output Duty Cycle (DC)
Figure 16. I/O Jitter
Figure 17. Cycle-to-cycle Jitter
Figure 18. Period Jitter
Figure 19. Output Transition Time Test Reference
tSK(O)
The pin-to-pin skew is defined as the worst case difference in propagation
delay between any similar delay path within a single device
VCC
VCC÷2
GND
VCC
VCC÷2
GND
t()
VCC
VCC÷2
GND
VCC
VCC÷2
GND
CCLK
FB_IN
tP
The time from the PLL controlled edge to the non controlled edge, divided
by the time between PLL controlled edges, expressed as a percentage
VCC
VCC÷2
GND
T0
DC = tP/T0 x 100%
TJIT() = |T0-T1mean|
CCLK
FB_IN
The deviation in t0 for a controlled edge with respect to a t0 mean
in a random sample of cycles
The variation in cycle time of a signal between adjacent cycles, over a random
sample of adjacent cycle pairs
TN
TJIT(CC) = |TN-TN+1|
TN+1
The deviation in cycle time of a signal with respect to the ideal period
over a random sample of cycles
TJIT(P) = |TN-1/f0|
T0
tF
tR
VCC=3.3V
2.4
0.55
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