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参数资料
| 型号： | MPC9893FAR2 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 9893 SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| 封装： | 7 X 7 MM, LQFP-48 |
| 文件页数： | 3/16页 |
| 文件大小： | 285K |
| 代理商： | MPC9893FAR2 |
MPC9893
TIMING SOLUTIONS
11
MOTOROLA
Figure 12. Output--to--output Skew tSK(O)
Figure 13. Propagation delay (t(), static phase
offset) test reference
Figure 14. Output Duty Cycle (DC)
The pin--to--pin skew is defined as the worst case difference
in propagation delay between any similar delay path within a
single device
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
VCC
VCC÷2
GND
VCC
VCC÷2
GND
tSK(O)
VCC
VCC÷2
GND
tP
T0
DC = tP/T0 x 100%
VCC
VCC÷2
GND
VCC
VCC÷2
GND
t()
CLK0,
CLK1
FB
TJIT() = |T0--T1mean|
CLK0, 1
FB
The deviation in t0 for a controlled edge with respect to a t0 mean in a
random sample of cycles
Figure 15. I/O Jitter
Figure 16. Cycle--to--cycle Jitter
Figure 17. Period Jitter
The variation in cycle time of a signal between adjacent cycles, over a
random sample of adjacent cycle pairs
The deviation in cycle time of a signal with respect to the ideal period over
a random sample of cycles
TN
TJIT(CC) = |TN--TN+1|
TN+1
TJIT(PER) = |TN--1/f0|
T0
tF
tR
VCC=3.3V
VCC=2.5V
2.4
1.8V
0.55
0.6V
Figure 18. Output Transition Time Test Reference
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