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| 型号： | MSC8126TVT6400 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 19/48页 |
| 文件大小： | 0K |
| 描述： | IC DSP QUAD 16B 400MHZ 431FCPBGA |
| 标准包装： | 60 |
| 系列： | StarCore |
| 类型： | SC140 内核 |
| 接口： | DSI，以太网，RS-232 |
| 时钟速率： | 400MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 1.436MB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.20V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 431-BFBGA，FCBGA |
| 供应商设备封装： | 431-FCPBGA（20x20） |
| 包装： | 托盘 |
| 配用： | MSC8126ADSE-ND - KIT ADVANCED DEV SYSTEM 8126 |
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Electrical Characteristics
Table 9. System Clock Parameters
Characteristic
Phase jitter between BCLK and CLKIN
CLKIN frequency
CLKIN slope
PLL input clock (after predivider)
Min
—
20
—
20
Max
0.3
3
100
Unit
ns
MHz
ns
MHz
PLL output frequency (VCO output)
? 400 MHz core
? 500 MHz core
800
1600
2000
MHz
MHz
MHz
CLKOUT frequency jitter 1
CLKOUT phase jitter 1 with CLKIN phase jitter of ±100 ps
Notes:
1.
Peak-to-peak.
2.
Not tested. Guaranteed by design.
2.5.4
Reset Timing
—
—
200
500
ps
ps
The MSC8126 has several inputs to the reset logic:
?
?
?
?
?
?
Power-on reset ( PORESET )
External hard reset ( HRESET )
External soft reset ( SRESET )
Software watchdog reset
Bus monitor reset
Host reset command through JTAG
All MSC8126 reset sources are fed into the reset controller, which takes different actions depending on the source of the reset.
The reset status register indicates the most recent sources to cause a reset. Table 10 describes the reset sources.
Table 10. Reset Sources
Name
Power-on reset
(PORESET)
External hard
reset (HRESET)
External soft reset
(SRESET)
Software
watchdog reset
Bus monitor reset
Host reset
command through
Direction
Input
Input/ Output
Input/ Output
Internal
Internal
Internal
Description
Initiates the power-on reset flow that resets the MSC8126 and configures various attributes of the
MSC8126. On PORESET, the entire MSC8126 device is reset. SPLL states is reset, HRESET and
SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The
clock mode (MODCK bits), reset configuration mode, boot mode, Chip ID, and use of either a DSI 64
bits port or a System Bus 64 bits port are configured only when PORESET is asserted.
Initiates the hard reset flow that configures various attributes of the MSC8126. While HRESET is
asserted , SRESET is also asserted. HRESET is an open-drain pin. Upon hard reset, HRESET and
SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The
most configurable features are reconfigured. These features are defined in the 32-bit hard reset
configuration word described in Hard Reset Configuration Word section of the Reset chapter in the
MSC8126 Reference Manual .
Initiates the soft reset flow. The MSC8126 detects an external assertion of SRESET only if it occurs
while the MSC8126 is not asserting reset. SRESET is an open-drain pin. Upon soft reset, SRESET is
driven, the SC140 extended cores are reset, and system configuration is maintained.
When the MSC8126 watchdog count reaches zero, a software watchdog reset is signalled. The
enabled software watchdog event then generates an internal hard reset sequence.
When the MSC8126 bus monitor count reaches zero, a bus monitor hard reset is asserted. The
enabled bus monitor event then generates an internal hard reset sequence.
When a host reset command is written through the Test Access Port (TAP), the TAP logic asserts the
soft reset signal and an internal soft reset sequence is generated.
the TAP
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 15
Freescale Semiconductor
19
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