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| 型号： | MSC8126TVT6400 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 40/48页 |
| 文件大小： | 0K |
| 描述： | IC DSP QUAD 16B 400MHZ 431FCPBGA |
| 标准包装： | 60 |
| 系列： | StarCore |
| 类型： | SC140 内核 |
| 接口： | DSI，以太网，RS-232 |
| 时钟速率： | 400MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 1.436MB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.20V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 431-BFBGA，FCBGA |
| 供应商设备封装： | 431-FCPBGA（20x20） |
| 包装： | 托盘 |
| 配用： | MSC8126ADSE-ND - KIT ADVANCED DEV SYSTEM 8126 |
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Hardware Design Considerations
3
Hardware Design Considerations
The following sections discuss areas to consider when the MSC8126 device is designed into a system.
3.1
Use the following guidelines for start-up and power-down sequences:
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Note:
Assert PORESET and TRST before applying power and keep the signals driven low until the power reaches the
required minimum power levels. This can be implemented via weak pull-down resistors.
CLKIN can be held low or allowed to toggle during the beginning of the power-up sequence. However, CLKIN must
start toggling before the deassertion of PORESET and after both power supplies have reached nominal voltage levels.
If possible, bring up V DD / V CCSYN and V DDH together. If it is not possible, raise V DD / V CCSYN first and then bring up
V DDH . V DDH should not exceed V DD / V CCSYN until V DD / V CCSYN reaches its nominal voltage level. Similarly, bring both
voltage levels down together. If that is not possible reverse the power-up sequence, with V DDH going down first and
then V DD / V CCSYN .
This recommended power sequencing for the MSC8126 is different from the MSC8102. See Section 2.5.2 for
start-up timing specifications.
External voltage applied to any input line must not exceed the I/O supply V DDH by more than 0.8 V at any time, including during
power-up. Some designs require pull-up voltages applied to selected input lines during power-up for configuration purposes.
This is an acceptable exception to the rule. However, each such input can draw up to 80 mA per input pin per device in the
system during start-up.
During the power-up sequence, if V DD rises before V DDH (see Figure 6 ), current can pass from the V DD supply through the
device ESD protection circuits to the V DDH supply. The ESD protection diode can allow this to occur when V DD exceeds V DDH
by more than 0.8 V. Design the power supply to prevent or minimize this effect using one of the following optional methods:
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Never allow V DD to exceed V DDH + 0.8V.
Design the V DDH supply to prevent reverse current flow by adding a minimum 10 Ω resistor to GND to limit the
current. Such a design yields an initial V DDH level of V DD – 0.8 V before it is enabled.
After power-up, V DDH must not exceed V DD / V CCSYN by more than 2.6 V.
3.2
When used as a drop-in replacement in MSC8102 applications or when implementing a new design, use the guidelines
described in Migrating Designs from the MSC8102 to the MSC8122 (AN2716) and the MSC8126 Design Checklist (AN3374
for optimal system performance. MSC8122 and MSC8126 Power Circuit Design Recommendations and Examples (AN2937)
provides detailed design information. See Section 2.5.2 for start-up timing specifications.
Figure 33 shows the recommended power decoupling circuit for the core power supply. The voltage regulator and the
decoupling capacitors should supply the required device current without any drop in voltage on the device pins. The voltage on
the package pins should not drop below the minimum specified voltage level even for a very short spikes. This can be achieved
by using the following guidelines:
40
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For the core supply, use a voltage regulator rated at 1.2 V with nominal rating of at least 3 A. This rating does not
reflect actual average current draw, but is recommended because it resists changes imposed by transient spikes and has
better voltage recovery time than supplies with lower current ratings.
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 15
Freescale Semiconductor
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| MSC8126VT8000 | 功能描述:IC DSP QUAD 16B 500MHZ 431FCPBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:StarCore 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
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