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| 型号： | MSC8126TVT6400 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 28/48页 |
| 文件大小： | 0K |
| 描述： | IC DSP QUAD 16B 400MHZ 431FCPBGA |
| 标准包装： | 60 |
| 系列： | StarCore |
| 类型： | SC140 内核 |
| 接口： | DSI，以太网，RS-232 |
| 时钟速率： | 400MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 1.436MB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.20V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 431-BFBGA，FCBGA |
| 供应商设备封装： | 431-FCPBGA（20x20） |
| 包装： | 托盘 |
| 配用： | MSC8126ADSE-ND - KIT ADVANCED DEV SYSTEM 8126 |
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Electrical Characteristics
2.5.6
DSI Timing
The timings in the following sections are based on a 20 pF capacitive load.
2.5.6.1 DSI Asynchronous Mode
Table 18. DSI Asynchronous Mode Timing
Attributes set-up time before strobe (HWBS[n]) assertion
No.
100
101
102
Characteristics
1
Attributes 1 hold time after data strobe deassertion
Read/Write data strobe deassertion width:
Min
1.5
1.3
Max
—
—
—
Unit
ns
ns
? DCR[HTAAD] = 1
— Consecutive access to the same DSI
— Different device with DCR[HTADT] = 01
— Different device with DCR[HTADT] = 10
— Different device with DCR[HTADT] = 11
? DCR[HTAAD] = 0
1.8 + T REFCLK
5 + T REFCLK
5 + (1.5 × T REFCLK )
5 + (2.5 × T REFCLK )
1.8 + T REFCLK
ns
ns
ns
ns
ns
103
104
105
106
107
Read data strobe deassertion to output data high impedance
Read data strobe assertion to output data active from high impedance
Output data hold time after read data strobe deassertion
Read/Write data strobe assertion to HTA active from high impedance
Output data valid to HTA assertion
—
2.0
2.2
2.2
3.2
8.5
—
—
—
—
ns
ns
ns
ns
ns
108
Read/Write data strobe assertion to HTA valid 2
? 1.1 V core
? 1.2 V core
—
—
7.4
6.7
ns
ns
109
Read/Write data strobe deassertion to output HTA high impedance.
—
6.5
ns
(DCR[HTAAD] = 0, HTA at end of access released at logic 0)
110
Read/Write data strobe deassertion to output HTA deassertion.
—
6.5
ns
(DCR[HTAAD] = 1, HTA at end of access released at logic 1)
111
Read/Write data strobe deassertion to output HTA high impedance.
(DCR[HTAAD] = 1, HTA at end of access released at logic 1
—
? DCR[HTADT] = 01
? DCR[HTADT] = 10
? DCR[HTADT] = 11
5 + T REFCLK
5 + (1.5 × T REFCLK )
5 + (2.5 × T REFCLK )
ns
ns
ns
112
201
Read/Write data strobe assertion width
Host data input set-up time before write data strobe deassertion
1.8 + T REFCLK
1.0
—
—
ns
ns
202
Host data input hold time after write data strobe deassertion
? 1.1 V core
? 1.2 V core
1.7
1.5
—
—
ns
ns
Notes:
28
1.
2.
3.
Attributes refers to the following signals: HCS, HA[11–29], HCID[0–4], HDST, HRW, HRDS, and HWBSn.
This specification is tested in dual-strobe mode. Timing in single-strobe mode is guaranteed by design.
All values listed in this table are tested or guaranteed by design.
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 15
Freescale Semiconductor
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