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参数资料
型号： MSC8126TVT6400
厂商： Freescale Semiconductor
文件页数： 46/48页
文件大小： 0K
描述： IC DSP QUAD 16B 400MHZ 431FCPBGA
标准包装： 60
系列： StarCore
类型： SC140 内核
接口： DSI，以太网，RS-232
时钟速率： 400MHz
非易失内存： 外部
芯片上RAM： 1.436MB
电压 - 输入/输出： 3.30V
电压 - 核心： 1.20V
工作温度： -40°C ~ 105°C
安装类型： 表面贴装
封装/外壳： 431-BFBGA，FCBGA
供应商设备封装： 431-FCPBGA（20x20）
包装： 托盘
配用： MSC8126ADSE-ND - KIT ADVANCED DEV SYSTEM 8126
Revision History
7
Revision History
Table 31 provides a revision history for this data sheet.
Table 31. Document Revision History
Revision
0
1
Date
May 2004
Jun. 2004
? Initial release.
? Updated timing number 32b.
? Updated DSI timing specifications.
Description
2
3
4
5
Sep 2004
Nov. 2004
Jan. 2005
May 2005
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
New orderable parts added with other core voltage and temperature options.
Updated thermal characteristics.
In Table 2-14, removed references to 30 pF.
Design guidelines and layout recommendations updated.
Added 500 MHz core and 166 MHz bus speed options.
Definitions of GPIO[27–28] updated.
Bus, TDM, and GPIO timing updated. I 2 C timing changed to GPIO timing.
GPIO[27–28] connections updated. MWBEn replaced with correct name HWBEn.
Design guidelines update.
Package type changed to FC-PBGA for all frequencies.
Low-voltage 3 00 MHz power changed to 1.1 V.
HRESET and SRESET definitions updated.
Undershoot and overshoot values added for V DDH .
RMII timing updated.
Design guidelines updated and reorganized.
Multiple AC timing specifications updated.
6
7
May 2005
Jul. 2005
? Multiple AC timing specifications updated.
? Multiple AC timing specifications updated.
8
9
10
11
12
13
Jul. 2005
Sep. 2005
Oct 2005
Apr 2006
Oct. 2006
Dec. 2007
?
?
?
?
?
?
?
?
?
?
?
?
AC specification table layout modified.
ETHTX_EN type and TRST description updated.
Package drawing updated.
Clock specifications updated.
Start-up sequence updated.
V DDH + 10% changed to V DDH + 8% in Figure 2-1 .
V DDH +20% changed to V DDH + 17% in Figure 2-1 .
Reset timing updated to reflect actual values in Table 2-11 .
Added new timings 17 and 18 for IRQ set time and pulse width in Table 2-13
Converted to new data sheet format.
Added PLL supply current to Table 5 in Section 2.4 .
Modified Figure 5 in Section 2.4 to make it clear that the time limits for undershoot referred to values
below –0.3 V and not GND.
?
?
?
?
?
Added cross-references between Sections 2.5.2 and Section 3.1 and 3.2 .
Added power-sequence guidelines to Sections 2.5.2 .
Added CLKIN jitter characteristic specifications to Table 9 .
Added additional guidelines to prevent reverse current to Section 3.1 .
Added connectivity guidelines for DSI in sliding windows mode to Section 3.3 .
14
May 2008
?
Changed V IL maximum and reference value to 0.8 V in Table 5 .
46
15
Dec 2008
? Clarified the wording of note 2 in Table 15 on p. 24.
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 15
Freescale Semiconductor
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