参数资料
型号: MSC8144E
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 数字信号处理
英文描述: 0-BIT, 150 MHz, OTHER DSP, PBGA783
封装: 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783
文件页数: 24/80页
文件大小: 2284K
代理商: MSC8144E
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0
Electrical Characteristics
Freescale Semiconductor
30
Table 9 provides the DDR capacitance when VDDDDR(typ) = 1.8 V.
2.6.1.2
DDR (2.5V) SDRAM DC Electrical Characteristics
Table 10 provides the recommended operating conditions for the DDR SDRAM component(s) of the MSC8144E when
VDDDDR(typ) = 2.5 V.
Table 11 provides the DDR capacitance when VDDDDR (typ) = 2.5 V.
Table 12 lists the current draw characteristics for MVREF.
Table 9. DDR2 SDRAM Capacitance for VDDDDR(typ) = 1.8 V
Parameter/Condition
Symbol
Min
Max
Unit
Input/output capacitance: DQ, DQS, DQS
CIO
68
pF
Delta input/output capacitance: DQ, DQS, DQS
CDIO
—0.5
pF
Note:
This parameter is sampled. VDDDDR = 1.8 V ± 0.090 V, f = 1 MHz, TA =25°C, VOUT = VDDDDR/2, VOUT (peak-to-peak) = 0.2 V.
Table 10. DDR SDRAM DC Electrical Characteristics for VDDDDR (typ) = 2.5 V
Parameter/Condition
Symbol
Min
Max
Unit
I/O supply voltage1
VDDDDR
2.3
2.7
V
I/O reference voltage2
MVREF
0.49
× VDDDDR
0.51
× VDDDDR
V
I/O termination voltage3
VTT
MVREF – 0.04
MVREF + 0.04
V
Input high voltage
VIH
MVREF + 0.15
VDD + 0.3
V
Input low voltage
VIL
–0.3
MVREF – 0.15
V
Output leakage current4
IOZ
–30
30
μA
Output high current (VOUT = 1.95 V)
IOH
–16.2
mA
Output low current (VOUT = 0.35 V)
IOL
16.2
mA
Notes:
1.
VDDDDR is expected to be within 50 mV of the DRAM VDD at all times.
2.
MVREF is expected to be equal to 0.5 × VDDDDR, and to track VDDDDR DC variations as measured at the receiver.
Peak-to-peak noise on MVREF may not exceed ±2% of the DC value.
3.
VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail should track variations in the DC level of VDDDDR.
4.
Output leakage is measured with all outputs are disabled, 0 V
V
OUT
V
DDDDR.
Table 11. DDR SDRAM Capacitance for VDDDDR (typ) = 2.5 V
Parameter/Condition
Symbol
Min
Max
Unit
Input/output capacitance: DQ, DQS
CIO
68
pF
Delta input/output capacitance: DQ, DQS
CDIO
—0.5
pF
Note:
This parameter is sampled. VDDDDR = 2.5 V ± 0.125 V, f = 1 MHz, TA = 25°C, VOUT = VDDDDR/2, VOUT (peak-to-peak) = 0.2 V.
Table 12. Current Draw Characteristics for MVREF
Parameter / Condition
Symbol
Min
Max
Unit
Current draw for MVREF
IMVREF
500
μA
Note:
The voltage regulator for MVREF must be able to supply up to 500 μA current.
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