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参数资料
| 型号： | MSC8144E |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 0-BIT, 150 MHz, OTHER DSP, PBGA783 |
| 封装： | 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783 |
| 文件页数： | 29/80页 |
| 文件大小： | 2284K |
| 代理商： | MSC8144E |
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Electrical Characteristics
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0
Freescale Semiconductor
35
The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs.
2.7.1
Start-Up Timing
Starting the device requires coordination among several input sequences including clocking, reset, and power. Section 2.7.2
describes the clocking characteristics. Section 2.7.3 describes the reset and power-up characteristics. You must use the
following guidelines when starting up an MSC8144E device:
PORESET and TRST must be asserted externally for the duration of the power-up sequence using the VDDIO (3.3 V)
supply. See Table 24 for timing. TRST deassertion does not have to be synchronized with PORESET deassertion.
During functional operation when JTAG is not used, TRST can be asserted and remain asserted after the power ramp.
Note:
For applications that use M3 memory, M3_RESET should replicate the PORESET sequence timing, but using the
CLKIN should start toggling at least 32 cycles before the PORESET deassertion to guarantee correct device operation
CLKIN and PCI_CLK_IN should either be stable low during the power-up of VDDIO supply and start their swings after
power-up or should swing within VDDIO range during VDDIO power-up., so their amplitude grows as VDDIO grows
during power-up.
Figure 7 shows a sequence in which VDDIO is raised after VDD and CLKIN begins to toggle with the raise of VDDIO supply.
Output low voltage, IOL= 3.2 mA
VOL
—0.4
V
Notes:
1.
See Figure 6 for undershoot and overshoot voltages.
2.
Not tested. Guaranteed by design.
Figure 6. Overshoot/Undershoot Voltage for VIH and VIL
Table 19. GPIO and CLKIN DC Electrical Characteristics (continued)
Characteristic
Symbol
Min
Max
Unit
GND
GND – 0.3 V
GND – 0.7 V
VIL
VIH
Must not exceed 10% of clock period
VDDIO + 17%
VDDIO + 5%
VDDIO
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MSC8144EC | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Quad Core Digital Signal Processor |
| MSC8144ESVT1000B | 制造商:Freescale Semiconductor 功能描述:DSP 32-BIT 1GHZ 1000MIPS 783-PIN FCBGA BOX - Trays 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA |
| MSC8144ESVT800A | 制造商:Freescale Semiconductor 功能描述:DSP 32BIT 800MHZ 800MIPS 783FCBGA - Trays |
| MSC8144ESVT800B | 制造商:Freescale Semiconductor 功能描述:DSP 32-BIT 800MHZ 800MIPS 783-PIN FCBGA EACH - Bulk 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA |
| MSC8144ETVT1000A | 制造商:Freescale Semiconductor 功能描述:DSP 32-BIT 1GHZ 1000MIPS 783-PIN FCBGA - Bulk |
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