参数资料
型号: MSC8144E
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 数字信号处理
英文描述: 0-BIT, 150 MHz, OTHER DSP, PBGA783
封装: 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783
文件页数: 50/80页
文件大小: 2284K
代理商: MSC8144E
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0
Freescale Semiconductor
54
2.7.9
Timer Timing
Figure 24 shows the timer input AC timing
2.7.10
Ethernet Timing
This section describes the AC electrical characteristics for the Ethernet interface.
There are programmable delay units (PDU) that should be programmed differently for each Interface to meet timing. There is
a general configuration register 4 (GCR4) used to configure the timing. For additional information, see the MSC8144E
Reference Manual.
2.7.10.1
Management Interface Timing
Table 44. Timer Timing
Characteristics
Symbol
Min
Unit
TIMERx frequency
TTMREFCLK
10.0
ns
TIMERx Input high phase
TTMCH
4.0
ns
TIMERx Output low phase
TTMCL
4.0
ns
Figure 24. Timer Timing
Table 45. Ethernet Controller Management Interface Timing
Characteristics
Symbol
Min
Max
Unit
ETHMDC clock pulse width high
tMDCH
32
ns
ETHMDC to ETHMDIO delay2
tMDKHDX
10
70
ns
ETHMDIO to ETHMDC rising edge set-up time
tMDDVKH
5—
ns
ETHMDC rising edge to ETHMDIO hold time
tMDDXKH
0—
ns
ETHMDC rise time.
tMDCR
—10
ns
ETHMDC fall time.
tMDHF
—10
ns
Notes:
1.
Typical ETHMDC frequency (fMDC) is 2.5 MHz with a 400 ns period (tMDC). The value depends on the source clock. For
example, for a source clock of 267 MHz, the maximum frequency is 8.3 MHz and the minimum frequency is 1.2 MHz. For a
375 MHz clock, the maximum frequency is 11.7 MHz and the minimum frequency is 1.7 MHz.
2.
The value depends on the source clock. For example, for a source clock of 267 MHz, the delay is 70 ns. For a source clock of
333 MHz, the delay is 58 ns.
TTMREFCLK
TTMCL
TTMCH
TIMERx (Input)
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