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参数资料
| 型号： | MSC8144E |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 0-BIT, 150 MHz, OTHER DSP, PBGA783 |
| 封装： | 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783 |
| 文件页数： | 31/80页 |
| 文件大小： | 2284K |
| 代理商： | MSC8144E |
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Electrical Characteristics
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0
Freescale Semiconductor
37
Table 22. Reset Sources
Table 23 summarizes the reset actions that occur as a result of the different reset sources.
Name
Direction
Description
Power-on reset
(PORESET)
Input
Initiates the power-on reset flow that resets the MSC8144E and configures various attributes of the
MSC8144E. On PORESET, the entire MSC8144E device is reset. All PLLs states is reset, HRESET
and SRESET are driven, the extended cores are reset, and system configuration is sampled. The
reset source and word are configured only when PORESET is asserted.
External hard
reset (HRESET)
Input/ Output
Initiates the hard reset flow that configures various attributes of the MSC8144E. While HRESET is
asserted, SRESET is also asserted. HRESET is an open-drain pin. Upon hard reset, HRESET and
SRESET are driven, the extended cores are reset, and system configuration is sampled. Note that
the RCW (reset Configuration Word) is not reloaded during HRESET assertion after out of power on
reset sequence. The reset configuration word is described in the Reset chapter in the MSC8144E
Reference Manual.
External soft reset
(SRESET)
Input/ Output
Initiates the soft reset flow. The MSC8144E detects an external assertion of SRESET only if it occurs
while the MSC8144E is not asserting reset. SRESET is an open-drain pin. Upon soft reset, SRESET
is driven, the extended cores are reset, and system configuration is maintained.
Host reset
command through
the TAP
Internal
When a host reset command is written through the Test Access Port (TAP), the TAP logic asserts the
soft reset signal and an internal soft reset sequence is generated.
Software
watchdog reset
Internal
When the MSC8144E watchdog count reaches zero, a software watchdog reset is signalled. The
enabled software watchdog event then generates an internal hard reset sequence.
RapidIO reset
Internal
When the RapidIO logic asserts the RapidIO hard reset signal, it generates an internal hard reset
sequence.
Software hard
reset
Internal
A hard reset sequence can be initialized by writing to a memory mapped register (RCR)
Software soft reset
Internal
A soft reset sequence can be initialized by writing to a memory mapped register (RCR)
Table 23. Reset Actions for Each Reset Source
Reset Action/Reset Source
Power-On Reset
(PORESET)
Hard Reset (HRESET)
Soft Reset (SRESET)
External only
External or Internal
(Software Watchdog,
Software or RapidIO)
External or
internal
Software
JTAG Command:
EXTEST, CLAMP, or
HIGHZ
Configuration pins sampled (Refer to
Section 2.7.3.2 for details).
Yes
NoNoNo
PLL state reset
Yes
No
Select reset configuration source
Yes
No
System reset configuration write
Yes
No
HRESET driven
Yes
No
IPBus modules reset (TDM, UART, SWT,
DDRC, IPBus master, GIC, HS, and GPIO)
Yes
SRESET driven
Yes
Depends on command
Extended cores reset
Yes
CLASS registers reset
Yes
Some
registers
Some registers
Timers, Performance Monitor
Yes
No
Packet Processor, PCI, DMA
Yes
Most
registers
Most registers
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相关代理商/技术参数 |
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| MSC8144EC | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Quad Core Digital Signal Processor |
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