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参数资料
| 型号： | MSC8144E |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 0-BIT, 150 MHz, OTHER DSP, PBGA783 |
| 封装： | 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783 |
| 文件页数： | 54/80页 |
| 文件大小： | 2284K |
| 代理商： | MSC8144E |
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MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0
Freescale Semiconductor
58
Figure 31. SMII Mode Signal Timing
2.7.10.6
RGMII AC Timing Specifications
Table 50 presents the RGMII AC timing specifications for applications requiring an on-board delayed clock.
Table 51 presents the RGMII AC timing specification for applications required non-delayed clock on board.
Table 50. RGMII with On-Board Delay AC Timing Specifications
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Data to clock output skew (at transmitter)
tSKEWT
-0.5
—
0.5
ns
Data to clock input skew (at receiver) 2
tSKEWR
0.9
—
2.6
ns
Clock cycle duration 3
tRGT
7.2
8.0
8.8
ns
Duty cycle for 1000Base-T 4, 5
tRGTH/tRGT
45
50
55
%
Duty cycle for 10BASE-T and 100BASE-TX 3, 5
tRGTH/tRGT
40
50
60
%
Rise time (20%–80%)
tRGTR
—
0.75
ns
Fall time (20%–80%)
tRGTF
—
0.75
ns
GTX_CLK125 reference clock period
tG12
6
—8.0
—
ns
GTX_CLK125 reference clock duty cycle
tG125H/tG125
47
—
53
%
Notes:
1.
At recommended operating conditions with LVDD of 2.5 V +/- 5%.
2.
This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns will
be added to the associated clock signal.
3.
For 10 and 100 Mbps, tRGT scales to 400 ns +/- 40 ns and 40 ns +/- 4 ns, respectively.
4.
Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long
as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned
between.
5.
Duty cycle reference is LVdd/2.
6.
This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.
7.
GCR4 should be programmed as 0x00001004.
Table 51. RGMII with No On-Board Delay AC Timing Specifications
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Data to clock output skew (at transmitter)
tSKEWT
0.9
—
2.6
ns
Data to clock input skew (at receiver) 2
tSKEWR
-0.5
—
0.5
ns
Clock cycle duration 3
tRGT
7.2
8.0
8.8
ns
Duty cycle for 1000Base-T 4, 5
tRGTH/tRGT
45
50
55
%
Duty cycle for 10BASE-T and 100BASE-TX 3, 5
tRGTH/tRGT
40
50
60
%
Rise time (20%–80%)
tRGTR
—
0.75
ns
Fall time (20%–80%)
tRGTF
—
0.75
ns
GTX_CLK125 reference clock period
tG12
6
—8.0
—
ns
Valid
ETHCLOCK
ETHSYNC_IN
ETHRXD
ETHSYNC
ETHTXD
Valid
tSMXR
tSMDXKH
tSMDVKH
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相关代理商/技术参数 |
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|---|---|
| MSC8144EC | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Quad Core Digital Signal Processor |
| MSC8144ESVT1000B | 制造商:Freescale Semiconductor 功能描述:DSP 32-BIT 1GHZ 1000MIPS 783-PIN FCBGA BOX - Trays 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA |
| MSC8144ESVT800A | 制造商:Freescale Semiconductor 功能描述:DSP 32BIT 800MHZ 800MIPS 783FCBGA - Trays |
| MSC8144ESVT800B | 制造商:Freescale Semiconductor 功能描述:DSP 32-BIT 800MHZ 800MIPS 783-PIN FCBGA EACH - Bulk 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA |
| MSC8144ETVT1000A | 制造商:Freescale Semiconductor 功能描述:DSP 32-BIT 1GHZ 1000MIPS 783-PIN FCBGA - Bulk |
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