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参数资料
| 型号： | MT18LSDT1672AY-13EXX |
| 元件分类： | DRAM |
| 英文描述： | 16M X 72 SYNCHRONOUS DRAM MODULE, 5.4 ns, DMA168 |
| 封装： | LEAD FREE, MO-161, DIMM-168 |
| 文件页数： | 2/25页 |
| 文件大小： | 553K |
| 代理商： | MT18LSDT1672AY-13EXX |
64MB x72, ECC, SR), 128MB (x72, ECC, DR)
168-PIN SDRAM UDIMM
09005aef807b3709
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD9_18C8_16x72AG.fm - Rev. E 6/04 EN
10
2004 Micron Technology, Inc.
NOTE:
1. For full-page accesses: y = 512
2. For a burst length of two, A1–A8 select the block of two
burst; A0 selects the starting column within the block.
3. For a burst length of four, A2–A8 select the block of
four burst; A0-A1 select the starting column within the
block.
4. For a burst length of eight, A3–A8 select the block of
eight burst; A0–A2 select the starting column within the
block.
5. For a full-page burst, the full row is selected and A0–A8
select the starting column.
6. Whenever a boundary of the block is reached within a
given sequence above, the following access wraps
within the block.
7. For a burst length of one, A0–A8 select the unique col-
umn to be accessed, and Mode Register bit M3 is
ignored.For a full-page burst, the full row is selected
and A0–A8 select the starting column.
Figure 6: CAS Latency Diagram
CAS Latency
The CAS latency is the delay, in clock cycles,
between the registration of a READ command and the
availability of the first piece of output data. The latency
can be set to two or three clocks.
If a READ command is registered at clock edge n,
and the latency is m clocks, the data will be available
by clock edge n + m. The DQs will start driving as a
result of the clock edge one cycle earlier (n + m - 1),
and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example,
assuming that the clock cycle time is such that all rele-
vant access times are met, if a READ command is regis-
tered at T0 and the latency is programmed to two
clocks, the DQs will start driving after T1 and the data
will be valid by T2, as shown in Figure 6, CAS Latency
cates the operating frequencies at which each CAS
latency setting can be used.
Reserved states should not be used as unknown
operation or incompatibility with future versions may
result.
Table 7:
Burst Definition Table
BURST
LENGTH
STARTING
COLUMN
ADDRESS
ORDER OF ACCESSES WITHIN
A BURST
TYPE =
SEQUENTIAL
TYPE =
INTERLEAVED
2
A0
00-1
0-1
11-0
1-0
4
A1
A0
0
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
1
3-0-1-2
3-2-1-0
8
A2 A1
A0
0
0-1-2-3-4-5-6-7
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Full
Page
(y)
n= A0-A9
(location 0-y)
Cn, Cn+1, Cn+2
Cn+3, Cn+4...
...Cn-1, Cn...
Not Supported
CLK
DQ
T2
T1
T3
T0
CAS Latency = 3
LZ
DOUT
tOH
t
COMMAND
NOP
READ
tAC
NOP
T4
NOP
DON’T CARE
UNDEFINED
CLK
DQ
T2
T1
T3
T0
CAS Latency = 2
LZ
DOUT
tOH
t
COMMAND
NOP
READ
tAC
NOP
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相关代理商/技术参数 |
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|---|---|
| MT18LSDT1672G-10EC2 | 制造商:Micron Technology Inc 功能描述:DRAM MOD SDRAM 1.125GBIT 168RDIMM - Trays |
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| MT18LSDT3272 | 制造商:Micron Technology Inc 功能描述:256MB 32MX72 SDRAM MODULE DIMM 3.3V REGISTERED - Trays |
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