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参数资料
| 型号： | MT18LSDT1672AY-13EXX |
| 元件分类： | DRAM |
| 英文描述： | 16M X 72 SYNCHRONOUS DRAM MODULE, 5.4 ns, DMA168 |
| 封装： | LEAD FREE, MO-161, DIMM-168 |
| 文件页数： | 25/25页 |
| 文件大小： | 553K |
| 代理商： | MT18LSDT1672AY-13EXX |
64MB x72, ECC, SR), 128MB (x72, ECC, DR)
168-PIN SDRAM UDIMM
09005aef807b3709
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD9_18C8_16x72AG.fm - Rev. E 6/04 EN
9
2004 Micron Technology, Inc.
Mode register bits M0–M2 specify the burst length,
M3 specifies the type of burst (sequential or inter-
leaved), M4–M6 specify the CAS latency, M7 and M8
specify the operating mode, M9 specifies the write
burst mode, and M10 and M11 are reserved for future
use. Address A12 (M12) is undefined but should be
driven LOW during loading of the mode register.
The mode register must be loaded when all device
banks are idle, and the controller must wait the speci-
fied time before initiating the subsequent operation.
Violating either of these requirements will result in
unspecified operation.
Burst Length
Read and write accesses to the SDRAM are burst ori-
ented, with the burst length being programmable, as
on page 9. The burst length determines the maximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 1, 2,
4, or 8 locations are available for both the sequential
and the interleaved burst types, and a full-page burst is
available for the sequential type. The full-page burst is
used in conjunction with the BURST TERMINATE
command to generate arbitrary burst lengths.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached, as shown in Table 7,
Burst Definition Table, on page 10. The block is
uniquely selected by A1–A8 when the burst length is
set to two; by A2–A8 when the burst length is set to
four; and by A3–A8 when the burst length is set to
eight. The remaining (least significant) address bit(s) is
(are) used to select the starting location within the
block. Full-page bursts wrap within the page if the
boundary is reached, as shown in Table 7, Burst Defini-
Burst Type
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is deter-
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 7, Burst
Figure 5: Mode Register Definition
Diagram
M3 = 0
1
2
4
8
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Operating Mode
Standard Operation
All other states reserved
0
-
0
-
Defined
-
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
2
3
Reserved
Burst Length
M0
0
1
0
1
0
1
0
1
Burst Length
CAS Latency
BT
A9
A7
A6
A5
A4
A3
A8
A2
A1
A0
Mode Register (Mx)
Address Bus
9
7
65
4
3
8
2
1
0
M1
0
1
0
1
M2
0
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
1
0
1
M6
0
1
M6-M0
M8
M7
Op Mode
A10
A11
10
11
Reserved* WB
0
1
Write Burst Mode
Programmed Burst Length
Single Location Access
M9
*Should program
M11, M10 = “0, 0”
to ensure compatibility
with future devices.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT18LSDT1672G-10EC2 | 制造商:Micron Technology Inc 功能描述:DRAM MOD SDRAM 1.125GBIT 168RDIMM - Trays |
| MT18LSDT1672G-133C2 | 制造商:Micron Technology Inc 功能描述:16M X 72 SYNCHRONOUS DRAM MODULE, 5.4 ns, DMA168 |
| MT18LSDT1672G-13EG3 | 制造商:Micron Technology Inc 功能描述:DRAM MOD SDRAM 1.125GBIT 168RDIMM - Trays |
| MT18LSDT3272 | 制造商:Micron Technology Inc 功能描述:256MB 32MX72 SDRAM MODULE DIMM 3.3V REGISTERED - Trays |
| MT18LSDT3272AG-10EB1 | 制造商:Micron Technology Inc 功能描述: |
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