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参数资料
型号： MT2VDDT832UY-75ZXX
元件分类： DRAM
英文描述： 8M X 32 DDR DRAM MODULE, 0.75 ns, DMA100
封装： LEAD FREE, DIMM-100
文件页数： 11/27页
文件大小： 420K
代理商： MT2VDDT832UY-75ZXX
32MB, 64MB (x32, SR)
100-PIN DDR UDIMM
pdf: 09005aef808ebdbc, source: 09005aef808e914b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD2C8_16x32UG.fm - Rev. D 9/04 EN
19
2004 Micron Technology, Inc. All rights reserved.
31. READs and WRITEs with auto precharge are not
allowed to be issued until tRAS (MIN) can be satis-
fied prior to the internal precharge command
being issued.
32. Any positive glitch to the nominal voltage must be
less than 1/3 of the clock and not more than
+400mV or 2.9 volts maximum, whichever is less.
Any negative glitch must be less than 1/3 of the
clock cycle and not exceed either -300mV or 2.2
volts minimum, whichever is more positive.
33. Normal Output Drive Curves:
a. The full variation in driver pull-down current
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 8,
Normal Output Pull-Down Characteristics.
b. The variation in driver pull-down current
within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve
of
Figure
8,
Normal
Output
Pull-Down Characteristics.
c. The full variation in driver pull-up current
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 9,
Normal Output Pull-Up Characteristics.
d. The variation in driver pull-up current within
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of Figure
9, Normal Output Pull-Up Characteristics.
e. The full variation in the ratio of the maximum
to minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature.
f. The full variation in the ratio of the nominal
pull-up to pull-down current should be unity
±10 percent, for device drain-to-source volt-
ages from 0.1V to 1.0V.
34. Reduced Output Drive Curves:
a. The full variation in driver pull-down current
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 10,
Reduced Output Pull-Down Characteristics,
on page 20.
b. The variation in driver pull-down current
within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure 10, Reduced Output Pull-Down
Characteristics, on page 20.
c. The full variation in driver pull-up current
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 11,
Reduced Output Pull-Up Characteristics, on
page 20.
d. The variation in driver pull-up current within
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of
Figure 11, Reduced Output Pull-Up Character-
istics, on page 20.
e. The full variation in the ratio of the maximum
to minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage.
f. The full variation in the ratio of the nominal
pull-up to pull-down current should be unity
±10 percent, for device drain-to-source volt-
ages from 0.1V to 1.0V.
35. The voltage levels used are derived from a mini-
mum VDD level and the referenced test load. In
practice, the voltage levels obtained from a prop-
erly terminated bus will provide significantly dif-
ferent voltage values.
36. VIH overshoot: VIH (MAX) = VDDQ + 1.5V for a
pulse width
≤ 3ns and the pulse width can not be
greater than 1/3 of the cycle rate. VIL undershoot:
VIL (MIN) = -1.5V for a pulse width
≤ 3ns and the
pulse width can not be greater than 1/3 of the
cycle rate.
37. VDD and VDDQ must track each other.
38. tHZ (MAX) will prevail over tDQSCK (MAX) +
tRPST (MAX) condition. tLZ (MIN) will prevail
over tDQSCK (MIN) + tRPRE (MAX) condition.
39. tRPST end point and tRPRE begin point are not
referenced to a specific voltage level but specify
when the device output is no longer driving
(tRPST), or begins driving (tRPRE).
40. During initialization, VDDQ, VTT, and VREF must
be equal to or less than VDD + 0.3V. Alternatively,
VTT may be 1.35V maximum during power up,
even if VDD/VDDQ are 0 volts, provided a mini-
mum of 42 ohms of series resistance is used
between the VTT supply and the input pin.
41. The current Micron part operates below the slow-
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
42. For the -6, -75Z, and -75 IDD3N is specified to be
35mA per DDR SDRAM device at 100 MHz.
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