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| 型号： | MT2VDDT832UY-75ZXX |
| 元件分类： | DRAM |
| 英文描述： | 8M X 32 DDR DRAM MODULE, 0.75 ns, DMA100 |
| 封装： | LEAD FREE, DIMM-100 |
| 文件页数： | 22/27页 |
| 文件大小： | 420K |
| 代理商： | MT2VDDT832UY-75ZXX |
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32MB, 64MB (x32, SR)
100-PIN DDR UDIMM
pdf: 09005aef808ebdbc, source: 09005aef808e914b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD2C8_16x32UG.fm - Rev. D 9/04 EN
4
2004 Micron Technology, Inc. All rights reserved.
Table 5:
Pin Descriptions
Refer to Pin Assignment Tables on page 3 for pin number and symbol information
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
32, 79, 81
WE#, CAS#, RAS#
Input
Command Inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
17, 18
CK0, CK0#
Input
Clock: CK, CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the
positive edge of CK,and negative edge of CK#. Output data
(DQ and DQS) is referenced to the crossings of CK and CK#.
70
CKE0
Input
Clock Enable: CKE HIGH activates and CKE LOW deactivates
the internal clock, input buffers and output drivers. Taking
CKE LOW provides PRECHARGE POWER-DOWN and SELF
REFRESH operations (all device banks idle), or ACTIVE POWER-
DOWN (row ACTIVE in any device bank).CKE is synchronous
for POWER-DOWN entry and exit, and for SELF REFRESH entry.
CKE is asynchronous for SELF REFRESH exit and for disabling
the outputs. CKE must be maintained HIGH throughout read
and write accesses. Input buffers (excluding CK, CK#, and CKE)
are disabled during POWER-DOWN. Input buffers (excluding
CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input
but will detect an LVCMOS LOW level after VDD is applied.
33
S0#
Input
Chip Selects: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
31, 78
BA0, BA1
Input
Bank Address: BA0 and BA1 define to which device bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
21 (64MB), 23, 24, 26-29, 71–
74, 76, 77
A0–A11
(32MB)
A0–A12
(64MB)
Input
Address Inputs: Provide the row address for ACTIVE
commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one device bank (A10 LOW, device
bank selected by BA0, BA1) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a MODE
REGISTER SET command. BA0 and BA1 define which mode
register (mode register or extended mode register) is loaded
during the LOAD MODE REGISTER command.
4, 12, 37, 45
DQS0–DQS3
Input/
Output
Data Strobe: Output with READ data, input with WRITE data.
DQS is edge-aligned with READ data, centered in WRITE data.
Used to capture data.
54, 62, 87, 95
DM0–DM3
Input
Data Write Mask. DM LOW allows WRITE operation. DM HIGH
blocks WRITE operation. DM lines do not affect READ
operation.
1, 3, 6, 7, 9,10, 13, 15, 34, 36,
39, 40, 42, 43, 46, 48, 51, 53,
56, 57, 59, 60, 63, 65, 84, 86,
89, 90, 92, 93, 96, 98
DQ0–DQ31
Input/
Output
Data I/Os: Data bus.
49
SA0
Input
Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
99
SDA
Input/
Output
Serial Presence-Detect Data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-
detect portion of the module.
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