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参数资料
| 型号： | MT2VDDT832UY-75ZXX |
| 元件分类： | DRAM |
| 英文描述： | 8M X 32 DDR DRAM MODULE, 0.75 ns, DMA100 |
| 封装： | LEAD FREE, DIMM-100 |
| 文件页数： | 13/27页 |
| 文件大小： | 420K |
| 代理商： | MT2VDDT832UY-75ZXX |
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32MB, 64MB (x32, SR)
100-PIN DDR UDIMM
pdf: 09005aef808ebdbc, source: 09005aef808e914b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD2C8_16x32UG.fm - Rev. D 9/04 EN
20
2004 Micron Technology, Inc. All rights reserved.
Figure 8: Normal Output
Pull-Down Characteristics
Figure 9: Normal Output Pull-Up
Characteristics
Figure 10: Reduced Output Pull-Down
Characteristics
Figure 11: Reduced Output Pull-Up
Characteristics
43. Random addressing changing and 50 percent of
data changing at every transfer.
44. Random addressing changing and 100 percent of
data at every transfer.
45. CKE must be active (high) during the entire time a
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
tREF later.
46. IDD2N specifies the DQ, DQS, and DM to be
driven to a valid high or low logic level. IDD2Q is
similar to IDD2F except IDD2Q specifies the
address and control inputs to remain stable.
Although IDD2F, IDD2N, and IDD2Q are similar,
IDD2F is “worst case.”
47. Whenever the operating frequency is altered, not
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles.
48. Leakage number reflects the worst case leakage
possible through the module pin, not what each
memory device contributes.
49. When an input signal is HIGH or LOW, it is
defined as a steady state logic HIGH or LOW.
50. The -6 speed grade will operate with tRAS (MIN) =
40ns and tRAS (MAX) = 120,000ns at any slower
frequency.
160
140
IOUT
(mA)
VOUT (V)
Nominal low
Minimum
Nominal
high
Maximum
120
100
80
60
40
20
0
0.0
0.5
1.0
1.5
2.0
2.5
VOUT (V)
0
-20
IOUT
(mA)
Nominal
low
Minimum
Nominal high
Maximum
-40
-60
-80
-100
-120
-140
-160
-180
-200
0.0
0.5
1.0
1.5
2.0
2.5
VDDQ - VOUT (V)
0
10
20
30
40
50
60
70
80
0.0
0.5
1.0
1.5
2.0
2.5
VOUT (V)
IOUT
(mA)
Nominal low
Minimum
Nominal high
Maximum
-80
-70
-60
-50
-40
-30
-20
-10
0
0.0
0.5
1.0
1.5
2.0
2.5
VDDQ - VOUT (V)
IOUT
(mA)
Minimum
Maximum
Nominal low
Nominal
high
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