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参数资料
| 型号： | MT2VDDT832UY-75ZXX |
| 元件分类： | DRAM |
| 英文描述： | 8M X 32 DDR DRAM MODULE, 0.75 ns, DMA100 |
| 封装： | LEAD FREE, DIMM-100 |
| 文件页数： | 5/27页 |
| 文件大小： | 420K |
| 代理商： | MT2VDDT832UY-75ZXX |
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32MB, 64MB (x32, SR)
100-PIN DDR UDIMM
pdf: 09005aef808ebdbc, source: 09005aef808e914b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD2C8_16x32UG.fm - Rev. D 9/04 EN
13
2004 Micron Technology, Inc. All rights reserved.
Table 12:
IDD Specifications and Conditions – 32MB Module
DDR SDRAM components only
Notes: 1–5, 8, 10, 14, 49; notes appear on pages 17–20; 0°C
≤ T
A ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V
MAX
PARAMETER/CONDITION
SYMBOL
-6
-75Z/-75
UNITS
NOTES
OPERATING CURRENT: One device bank; Active-Precharge;
tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs
changing once per clock cyle; Address and control inputs
changing once every two clock cycles
IDD0
250
220
mA
20, 43
OPERATING CURRENT: One device bank; Active -Read Precharge;
Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address
and control inputs changing once per clock cycle
IDD1
270
240
mA
20, 43
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks
idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW)
IDD2P
6
mA
21, 28, 45
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK =
tCK MIN; CKE = HIGH; Address and other control inputs changing
once per clock cycle. VIN = VREF for DQ, DQS, and DM
IDD2F
90
mA
46
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank
active; Power-down mode; tCK = tCK (MIN); CKE = LOW
IDD3P
50
mA
21, 28, 45
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device
bank; Active-Precharge; tRC = tRAS (MAX);tCK = tCK (MIN); DQ,
DM and DQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
IDD3N
100
mA
20
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One
bank active; Address and control inputs changing once per clock
cycle; tCK = tCK (MIN); IOUT = 0mA
IDD4R
280
260
mA
20, 43
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
device bank active; Address and control inputs changing once
per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs
changing twice per clock cycle
IDD4W
280
250
mA
20
AUTO REFRESH CURRENT
tREFC = tRFC (MIN)
IDD5
530
440
mA
20, 45
tREFC = 15.625s
IDD5A
10
mA
24, 45
SELF REFRESH CURRENT: CKE
≤ 0.2V
IDD6
64
mA
9
OPERATING CURRENT: Four device bank interleaving READs
(BL = 4) with auto precharge, tRC = tRC (MIN); tCK = tCK (MIN);
Address and control inputs change only during Active READ or
WRITE commands
IDD7
710
660
mA
20, 44
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