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| 型号： | MT2VDDT832UY-75ZXX |
| 元件分类： | DRAM |
| 英文描述： | 8M X 32 DDR DRAM MODULE, 0.75 ns, DMA100 |
| 封装： | LEAD FREE, DIMM-100 |
| 文件页数： | 7/27页 |
| 文件大小： | 420K |
| 代理商： | MT2VDDT832UY-75ZXX |
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32MB, 64MB (x32, SR)
100-PIN DDR UDIMM
pdf: 09005aef808ebdbc, source: 09005aef808e914b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD2C8_16x32UG.fm - Rev. D 9/04 EN
15
2004 Micron Technology, Inc. All rights reserved.
Table 14:
Capacitance
Note: 11; notes appear on pages 17–20
PARAMETER
SYMBOL
MIN
MAX
UNITS
Input/Output Capacitance: DQ, DQS, DM
CIO
45
pF
Input Capacitance: CK, CK#
CI1
79
pF
Input Capacitance: Command and Address, S#, CKE
CI2
46
pF
Table 15:
DDR SDRAM Component Electrical Characteristics and Recommended AC
Operating Conditions
Notes: 1–5, 12–15, 29, 49, 50; notes appear on pages 17–20; 0°C
≤ T
A ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V
AC CHARACTERISTICS
-6
-75/75Z
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS NOTES
Access window of DQ from CK/CK#
tAC
-0.7
+0.7
-0.75
+0.75
ns
CK high-level width
tCH
0.45
0.55
0.45
0.55
tCK
26
CK low-level width
tCL
0.45
0.55
0.45
0.55
tCK
26
Clock cycle time
CL = 2.5
tCK (2.5)
6
13
7.5
13
ns
41, 47
CL = 2
tCK (2)
7.5
13
10
13
ns
41, 47
DQ and DM input hold time relative to DQS
tDH
0.45
0.5
ns
23, 27
DQ and DM input setup time relative to DQS
tDS
0.45
0.5
ns
23, 27
DQ and DM input pulse width (for each input)
tDIPW
1.75
ns
27
Access window of DQS from CK/CK#
tDQSCK
-0.6
+0.6
-0.75
+0.75
ns
DQS input high pulse width
tDQSH
0.35
tCK
DQS input low pulse width
tDQSL
0.35
tCK
DQS-DQ skew, DQS to last DQ valid, per group, per access
tDQSQ
0.45
0.5
ns
22, 23
Write command to first DQS latching transition
tDQSS
0.75
1.25
0.75
1.25
tCK
DQS falling edge to CK rising - setup time
tDSS
0.2
tCK
DQS falling edge from CK rising - hold time
tDSH
0.2
tCK
Half clock period
tHP
tCH,tCL
ns
30
Data-out high-impedance window from CK/CK#
tHZ
+0.70
+0.75
ns
16, 38
Data-out low-impedance window from CK/CK#
tLZ
-0.7
-0.75
ns
16, 38
Address and control input hold time (fast slew rate)
tIH
F
0.75
.90
ns
12
Address and control input setup time (fast slew rate)
tIS
F
0.75
.90
ns
12
Address and control input hold time (slow slew rate)
tIH
S
0.8
1
ns
12
Address and control input setup time (slow slew rate)
tIS
S
0.8
1
ns
12
Address and Control input pulse width (for each input)
tIPW
2.2
ns
LOAD MODE REGISTER command cycle time
tMRD
12
15
ns
DQ-DQS hold, DQS to first DQ to go non-valid, per access
tQH
tHP -
tQHS
tHP -
tQHS
ns
22, 23
Data hold skew factor
tQHS
0.6
0.75
ns
ACTIVE to PRECHARGE command
tRAS
42
70,000
40
120,000
ns
31
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