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参数资料
| 型号： | MT2VDDT832UY-75ZXX |
| 元件分类： | DRAM |
| 英文描述： | 8M X 32 DDR DRAM MODULE, 0.75 ns, DMA100 |
| 封装： | LEAD FREE, DIMM-100 |
| 文件页数： | 8/27页 |
| 文件大小： | 420K |
| 代理商： | MT2VDDT832UY-75ZXX |
第1页第2页第3页第4页第5页第6页第7页当前第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页
32MB, 64MB (x32, SR)
100-PIN DDR UDIMM
pdf: 09005aef808ebdbc, source: 09005aef808e914b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD2C8_16x32UG.fm - Rev. D 9/04 EN
16
2004 Micron Technology, Inc. All rights reserved.
ACTIVE to READ with Auto precharge command
tRAP
15
20
ns
ACTIVE to ACTIVE/AUTO REFRESH command period
tRC
60
65
ns
AUTO REFRESH command period
tRFC
72
75
ns
45
ACTIVE to READ or WRITE delay
tRCD
15
20
ns
PRECHARGE command period
tRP
15
20
ns
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
39
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
39
ACTIVE bank a to ACTIVE bank b command
tRRD
12
15
ns
DQS write preamble
tWPRE
0.25
tCK
DQS write preamble setup time
tWPRES
0
ns
18, 19
DQS write postamble
tWPST
0.4
0.6
0.4
0.6
tCK
17
Write recovery time
tWR
15
ns
Internal WRITE to READ command delay
tWTR
11
tCK
Data valid output window
na
tQH -tDQSQ
ns
22
REFRESH to REFRESH command interval
32MB
tREFC
140
140.6
s
21
64MB
70.3
s
Average periodic refresh interval
32MB
tREFI
15.6
s
21
64MB
7.8
s
Terminating voltage delay to VDD
tVTD
00
ns
Exit SELF REFRESH to non-READ command
tXSNR
75
ns
Exit SELF REFRESH to READ command
tXSRD
200
tCK
Table 15:
DDR SDRAM Component Electrical Characteristics and Recommended AC
Operating Conditions (Continued)
Notes: 1–5, 12–15, 29, 49, 50; notes appear on pages 17–20; 0°C
≤ T
A ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V
AC CHARACTERISTICS
-6
-75/75Z
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS NOTES
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