参数资料
型号: MT48LC16M4A2
厂商: Micron Technology, Inc.
元件分类: DC/DC变换器
英文描述: RSD Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 24V; Output Voltage (Vdc): 3.3V; Power: 1W; 1kVDC and 3kVDC Isolation Options; Approved for Medical Applications; Suitable for Automated Assembly; 8, 10 and 12 pin Pinning Style Options; Optional Continuous Short Circuit Protected; Efficiency to 85%
中文描述: 同步DRAM
文件页数: 13/55页
文件大小: 1458K
代理商: MT48LC16M4A2
13
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2003, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
AUTO REFRESH
AUTO REFRESH is used during normal operation of
the SDRAM and is analagous to CAS#-BEFORE-RAS#
(CBR) REFRESH in conventional DRAMs. This com-
mand is nonpersistent, so it must be issued each time
a refresh is required. All active banks must be
PRECHARGED prior to issuing an AUTO REFRESH com-
mand. The AUTO REFRESH command should not be
issued until the minimum tRP has been met after the
PRECHARGE command as shown in the operation sec-
tion.
The addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care”
during an AUTO REFRESH command. The 64Mb
SDRAM requires 4,096 AUTO REFRESH cycles every
64ms (
t
REF), regardless of width option. Providing a
distributed AUTO REFRESH command every 15.625μs
will meet the refresh requirement and ensure that each
row is refreshed. Alternatively, 4,096 AUTO REFRESH
commands can be issued in a burst at the minimum
cycle rate (
t
RC), once every 64ms.
SELF REFRESH
The SELF REFRESH command can be used to retain
data in the SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the
SDRAM retains data without external clocking.
The SELF REFRESH command is initiated like an AUTO
REFRESH command except CKE is disabled (LOW).
Once the SELF REFRESH command is registered, all
the inputs to the SDRAM become “Don’t Care,” with
the exception of CKE, which must remain LOW.
Once self refresh mode is engaged, the SDRAM pro-
vides its own internal clocking, causing it to perform its
own AUTO REFRESH cycles. The SDRAM must remain
in self refresh mode for a minimum period equal to
t
RAS and may remain in self refresh mode for an indefi-
nite period beyond that.
The procedure for exiting self refresh requires a se-
quence of commands. First, CLK must be stable (stable
clock is defined as a signal cycling within timing con-
straints specified for the clock pin) prior to CKE going
back HIGH. Once CKE is HIGH, the SDRAM must have
NOP commands issued (a minimum of two clocks) for
t
XSR, because time is required for the completion of
any internal refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH
commands must be issued every 15.625μs or less as
both SELF REFRESH and AUTO REFRESH utilize the
row refresh counter.
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