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参数资料
型号： MT48V4M32LFFC
厂商： Micron Technology, Inc.
英文描述： SYNCHRONOUS DRAM
中文描述： 同步DRAM
文件页数： 1/61页
文件大小： 1400K
代理商： MT48V4M32LFFC
1
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
128Mb: x16, x32
MOBILE SDRAM
ADVANCE
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PUROPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION AND DATA SHEET SPECIFICATIONS.
8 Meg x 16
2 Meg x 16 x 4 banks 1 Meg x 32 x 4 banks
4K
4K (A0–A11)
4 (BA0, BA1)
512 (A0–A8)
4 Meg x 32
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
4K
4K (A0–A11)
4 (BA0, BA1)
256 (A0–A7)
SYNCHRONOUS
DRAM
MT48LC8M16LFFF, MT48V8M16LFFF – 2 Meg x 16 x 4 banks
MT48LC4M32LFFC , MT48V4M32LFFC – 1 Meg x 32 x 4 banks
For the latest data sheet revisions, please refer to the Micron Web
www.micron.com/dramds
PIN ASSIGNMENT (Top View)
54-Ball VFBGA
FEATURES
Temperature Compensated Self Refresh (TCSR)
Fully synchronous; all signals registered on positive
edge of system clock
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable burst lengths: 1, 2, 4, 8, or full page
Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
Self Refresh Mode; standard and low power
64ms, 4,096-cycle refresh
LVTTL-compatible inputs and outputs
Low voltage power supply
Partial Array Self Refresh power-saving mode
Operating Temperature Range
Industrial (-40
o
C to +85
o
C)
OPTIONS
V
DD
/V
DD
Q
3.3V/3.3V
2.5V/2.5V or 1.8V
Configurations
8 Meg x 16 (2 Meg x 16 x 4 banks)
4 Meg x 32 (1 Meg x 32 x 4 banks)
Package/Ball out
Plastic Package
54-ball FBGA (8mm x 9mm)(x16 only)
90-ball FBGA (11mm x 13mm)
Timing (Cycle Time)
8ns @ CL = 3 (125 MHz)
10ns @ CL = 3 (100 MHz)
MARKING
LC
V
8M16
4M32
FF
1
FC
1
-8
-10
Part Number Example:
MT48V8M16LFFC-8
NOTE
: 1. See page 61 for FBGA/VFBGA Device Marking
Table.
KEY TIMING PARAMETERS
SPEED
GRADE FREQUENCY CL=1* CL=2* CL=3*
-8
125 MHz
-10
100 MHz
-8
100 MHz
-10
83 MHz
-8
50 MHz
-10
40 MHz
CLOCK
ACCESS TIME
t
RCD
t
RP
–
–
–
–
–
–
7ns
7ns
–
–
–
–
20ns
20ns
20ns
20ns
20ns
20ns
20ns
20ns
20ns
20ns
20ns
20ns
8ns
8ns
–
–
19ns
22ns
*CL = CAS (READ) latency
A
B
C
D
E
F
G
H
J
1
2
3
4
5
6
7
8
Top View
(Ball Down)
V
SS
DQ14
DQ12
DQ10
DQ8
UDQM
NC/A12
A8
V
SS
DQ15
DQ13
DQ11
DQ9
NC
CLK
A11
A7
A5
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
CKE
A9
A6
A4
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
CAS#
BA0
A0
A3
DQ0
DQ2
DQ4
DQ6
LDQM
RAS#
BA1
A1
A2
V
DD
DQ1
DQ3
DQ5
DQ7
WE#
CS#
A10
V
DD
9
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