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参数资料
| 型号： | MT48V4M32LFFC |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | SYNCHRONOUS DRAM |
| 中文描述： | 同步DRAM |
| 文件页数： | 39/61页 |
| 文件大小： | 1400K |
| 代理商： | MT48V4M32LFFC |
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39
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
128Mb: x16, x32
MOBILE SDRAM
ADVANCE
14. Timing actually specified by
t
CKS; clock(s) specified
as a reference only at minimum cycle rate.
15. Timing actually specified by
t
WR plus
t
RP; clock(s)
specified as a reference only at minimum cycle rate.
16. Timing actually specified by
t
WR.
17. Required clocks are specified by JEDEC functionality
and are not dependent on any timing parameter.
18. The I
DD
current will increase or decrease propor-
tionally according to the amount of frequency alter-
ation for the test condition.
19. Address transitions average one transition every two
clocks.
20. CLK must be toggled a minimum of two times during
this period.
21. Based on
t
CK =8ns for -8 and
t
CK =10ns for -10.
22. V
IH
overshoot: V
IH
(MAX) = V
DD
Q + 2V for a pulse width
≤
3ns, and the pulse width cannot be greater than one
third of the cycle rate. V
IL
undershoot: V
IL
(MIN) = -2V
for a pulse width
≤
3ns.
23. The clock frequency must remain constant (stable
clock is defined as a signal cycling within timing
constraints specified for the clock pin) during access
or precharge states (READ, WRITE, including
t
WR,
and PRECHARGE commands). CKE may be used to
reduce the data rate.
24. Auto precharge mode only. The precharge timing
budget (
t
RP) begins at 7ns for -8 after the first clock
delay, after the last WRITE is executed. May not ex-
ceed limit set for precharge mode.
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27.
t
AC for -8 at CL = 3 with no load is 7ns and is guaran-
teed by design.
28. Parameter guaranteed by design.
29. PC100 specifies a maximum of 4pF.
30. PC100 specifies a maximum of 5pF.
31. PC100 specifies a maximum of 6.5pF.
32. For -8, CL = 2 and
t
CK = 10ns; for -10, CL = 3 and
t
CK =10ns.
33. CKE is HIGH during refresh command period
t
RFC (MIN) else CKE is LOW. The I
DD
6 limit is actu-
ally a nominal value and does not result in a fail
value.
NOTES
1.
All voltages referenced to V
SS
.
2.
This parameter is sampled. V
DD
, V
DD
Q = +3.3V;
f = 1 MHz, T
= 25°C; pin under test biased at 1.4V.
3.
I
DD
is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
4.
Enables on-chip refresh and address counters.
5.
The minimum specifications are used only to
indicate cycle time at which proper operation over
the full temperature range (-40°C
≤
T
A
≤
+85°C for
IT parts) is ensured.
6.
An initial pause of 100μs is required after power-up,
followed by two AUTO REFRESH commands, before
proper device operation is ensured. (V
DD
and V
DD
Q
must be powered up simultaneously. V
SS
and V
SS
Q
must be at same potential.) The two AUTO REFRESH
command wake-ups should be repeated any time
the
t
REF refresh requirement is exceeded.
7.
AC characteristics assume
t
T = 1ns.
8.
In addition to meeting the transition rate specifica-
tion, the clock and CKE must transit between V
IH
and
V
IL
(or between V
IL
and V
IH
) in a monotonic manner.
9.
Outputs measured for 3.3V at1.5V or 2.5V at 1.25V
with equivalent load:
10.
t
HZ defines the time at which the output achieves the
open circuit condition; it is not a reference to V
OH
or
V
OL
. The last valid data element will meet
t
OH before
going High-Z.
11. AC timing and I
DD
tests have V
IL
and V
IH
, with timing
referenced to V
IH
/2 = crossover point. If the input
transition time is longer than t
(MAX), then the
timing is referenced at V
IL
(MAX) and V
IH
(MIN) and
no longer at the V
IH
/2 crossover point.
12. Other input signals are allowed to transition no more
than once every two clocks and are otherwise at valid
V
IH
or V
IL
levels.
13. I
DD
specifications are tested after the device is prop-
erly initialized.
Q
30pF
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