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参数资料
| 型号： | MT48LC16M4A2 |
| 厂商： | Micron Technology, Inc. |
| 元件分类： | DC/DC变换器 |
| 英文描述： | RSD Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 24V; Output Voltage (Vdc): 3.3V; Power: 1W; 1kVDC and 3kVDC Isolation Options; Approved for Medical Applications; Suitable for Automated Assembly; 8, 10 and 12 pin Pinning Style Options; Optional Continuous Short Circuit Protected; Efficiency to 85% |
| 中文描述： | 同步DRAM |
| 文件页数： | 14/55页 |
| 文件大小： | 1458K |
| 代理商： | MT48LC16M4A2 |
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14
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2003, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
Operation
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be is-
sued to a bank within the SDRAM, a row in that bank
must be “opened.” This is accomplished via the AC-
TIVE command, which selects both the bank and the
row to be activated (see Figure 3).
After opening a row (issuing an ACTIVE command),
a READ or WRITE command may be issued to that row,
subject to the
t
RCD specification.
t
RCD (MIN) should
be divided by the clock period and rounded up to the
next whole number to determine the earliest clock edge
after the ACTIVE command on which a READ or WRITE
command can be entered. For example, a
t
RCD specifi-
cation of 20ns with a 125 MHz clock (8ns period) results
in 2.5 clocks, rounded to 3. This is reflected in Figure 4,
which covers any case where 2 <
t
RCD (MIN)/
t
CK
(The same procedure is used to convert other specifi-
cation limits from time units to clock cycles).
A subsequent ACTIVE command to a different row
in the same bank can only be issued after the previous
active row has been “closed” (precharged). The mini-
mum time interval between successive ACTIVE com-
mands to the same bank is defined by
t
RC.
A subsequent ACTIVE command to another bank
can be issued while the first bank is being accessed,
which results in a reduction of total row-access over-
head. The minimum time interval between successive
ACTIVE commands to different banks is defined by
t
RRD.
3.
Figure 4
Example: Meeting
t
RCD (MIN) When 2 <
t
RCD (MIN)/
t
CK < 3
CLK
T2
T1
T3
T0
t
COMMAND
NOP
ACTIVE
READ or
WRITE
T4
NOP
RCD
DON’T CARE
CS#
WE#
CAS#
RAS#
CKE
CLK
A0–A10, A11
ROW
ADDRESS
HIGH
BA0, BA1
BANK
ADDRESS
Figure 3
Activating a Specific Row in a
Specific Bank
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48LC16M4A2_99 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:SYNCHRONOUS DRAM |
| MT48LC16M4A2TG | 制造商:MICRON 制造商全称:Micron Technology 功能描述:SYNCHRONOUS DRAM |
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