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参数资料
| 型号： | MT48LC8M16LFF4-10IT:G |
| 元件分类： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54 |
| 封装： | 8 X 8 MM, VFBGA-54 |
| 文件页数： | 35/80页 |
| 文件大小： | 2775K |
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PDF: 09005aef807f4885/Source: 09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
40
2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 Mobile SDRAM
READs
Figure 28:
Power-Down
CLOCK SUSPEND
The clock suspend mode occurs when a column access/burst is in progress and CKE is
registered low. In the clock suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive
clock edge is suspended. Any command or data present on the input pins at the time of a
suspended internal clock edge is ignored; any data present on the DQ pins remains
driven; and burst counters are not incremented as long as the clock is suspended. (See
examples in Figure 29 and in Figure 30 on page 41.)
Figure 29:
Clock Suspend During WRITE Burst
Notes:
1. For this example, burst length = 4 or greater, and DM is LOW.
Clock suspend mode is exited by registering CKE HIGH; the internal clock and related
operation will resume on the subsequent positive clock edge.
DON’T CARE
tRAS
tRCD
tRC
All banks idle
Input buffers gated off
Exit power-down mode.
(
)
(
)
(
)
(
)
(
)
(
)
tCKS
> tCKS
COMMAND
NOP
ACTIVE
Enter power-down mode.
NOP
CLK
CKE
(
)
(
)
(
)
(
)
DON’T CARE
DIN
COMMAND
ADDRESS
WRITE
BANK,
COL n
DIN
n
NOP
CLK
T2
T1
T4
T3
T5
T0
CKE
INTERNAL
CLOCK
NOP
DIN
n + 1
DIN
n + 2
TRANSITIONING DATA
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| MT48LC8M16LFF4-8XT | 8M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54 |
| MT48LC8M16LFTG-10XT:G | 8M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48LC8M16LFF4-75M IT | 制造商:Micron Technology Inc 功能描述:DRAM CHIP MOBILE SDRAM 128MBIT 3.3V 54FBGA - Trays |
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