- 您现在的位置：买卖IC网 > PDF目录187166 > MT48LC8M16LFF4-10IT:G 8M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54 PDF资料下载
参数资料
| 型号： | MT48LC8M16LFF4-10IT:G |
| 元件分类： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54 |
| 封装： | 8 X 8 MM, VFBGA-54 |
| 文件页数： | 38/80页 |
| 文件大小： | 2775K |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页当前第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页
PDF: 09005aef807f4885/Source: 09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
43
2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 Mobile SDRAM
READs
Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
interrupt a WRITE on bank n when registered. The precharge to bank n will begin
after tWR is met, where tWR begins when the WRITE to bank m is registered. The last
valid data WRITE to bank n will be data registered 1 clock prior to a WRITE to bank m
Figure 33:
WRITE With Auto Precharge Interrupted by a READ
Notes:
1. DQM is LOW.
Figure 34:
WRITE With Auto Precharge Interrupted by a WRITE
Notes:
1. DQM is LOW.
DON’T CARE
CLK
DQ
T2
T1
T4
T3
T6
T5
T0
COMMAND
WRITE - AP
BANK n
NOP
DIN
a + 1
DIN
a
NOP
T7
BANK n
BANK m
ADDRESS
BANK n,
COL a
BANK m,
COL d
READ - AP
BANK m
Internal
States
t
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
Precharge
Page Active
READ with Burst of 4
t
tRP - BANK m
DOUT
d
DOUT
d + 1
CL = 3 (BANK m)
RP - BANK n
WR - BANK n
TRANSITIONING DATA
DON’T CARE
CLK
DQ
T2
T1
T4
T3
T6
T5
T0
COMMAND
WRITE - AP
BANK n
NOP
DIN
d + 1
DIN
d
DIN
a + 1
DIN
a + 2
DIN
a
DIN
d + 2
DIN
d + 3
NOP
T7
BANK n
BANK m
ADDRESS
NOP
BANK n,
COL a
BANK m,
COL d
WRITE - AP
BANK m
Internal
States
t
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
Precharge
Page Active
WRITE with Burst of 4
Write-Back
WR - BANK n
tRP - BANK n
t WR - BANK m
TRANSITIONING DATA
相关PDF资料 |
PDF描述 |
|---|---|
| MT48V8M16LFF4-10:G | 8M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54 |
| MT48LC8M16LFF4-10 | 8M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54 |
| MT48LC8M16LFF4-8XT | 8M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54 |
| MT48LC8M16LFTG-10XT:G | 8M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| MT4C1024DJ-6IT | 1M X 1 FAST PAGE DRAM, 60 ns, PDSO20 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48LC8M16LFF4-75M IT | 制造商:Micron Technology Inc 功能描述:DRAM CHIP MOBILE SDRAM 128MBIT 3.3V 54FBGA - Trays |
发布紧急采购，3分钟左右您将得到回复。