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参数资料
| 型号： | MT48LC8M16LFF4-10IT:G |
| 元件分类： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54 |
| 封装： | 8 X 8 MM, VFBGA-54 |
| 文件页数： | 37/80页 |
| 文件大小： | 2775K |
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PDF: 09005aef807f4885/Source: 09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
42
2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 Mobile SDRAM
READs
Figure 31:
READ With Auto Precharge Interrupted by a READ
Notes:
1. DQM is LOW, BL = 4 or greater, and CL = 3.
Figure 32:
READ With Auto Precharge Interrupted by a WRITE
Notes:
1. DQM is HIGH at T2 to prevent DOUT a + 1 from contending with DIN d at T4.
WRITE with Auto Precharge
Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
rupt a WRITE on bank n when registered, with the data-out appearing CL later. The
precharge to bank n will begin after tWR is met, where tWR begins when the READ to
bank m is registered. The last valid WRITE to bank n will be data-in registered 1 clock
prior to the READ to bank m (Figure 33 on page 43).
DON’T CARE
CLK
DQ
DOUT
a
T2
T1
T4
T3
T6
T5
T0
COMMAND
READ - AP
BANK n
NOP
DOUT
a + 1
DOUT
d
DOUT
d + 1
NOP
T7
BANK n
CL = 3 (BANK m)
BANK m
ADDRESS
Idle
NOP
BANK n,
COL a
BANK m,
COL d
READ - AP
BANK m
Internal
States
t
Page Active
READ with Burst of 4
Interrupt Burst, Precharge
Page Active
READ with Burst of 4
Precharge
RP - BANK n
tRP - BANK m
CL = 3 (BANK n)
TRANSITIONING DATA
CLK
DQ
DOUT
a
T2
T1
T4
T3
T6
T5
T0
COMMAND
NOP
DIN
d
DIN
d + 2
DIN
d + 3
NOP
T7
BANK n
BANK m
ADDRESS
Idle
NOP
DQM
BANK n,
COL a
BANK m,
COL d
WRITE - AP
BANK m
Internal
States
t
Page
Active
READ with Burst of 4
Interrupt Burst, Precharge
Page Active
WRITE with Burst of 4
Write-Back
RP - BANK n
t WR - BANK m
CAS Latency = 3 (BANK n)
READ - AP
BANK n
1
DON’T CARE
TRANSITIONING DATA
DIN
d + 1
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相关代理商/技术参数 |
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|---|---|
| MT48LC8M16LFF4-75M IT | 制造商:Micron Technology Inc 功能描述:DRAM CHIP MOBILE SDRAM 128MBIT 3.3V 54FBGA - Trays |
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