参数资料
型号: MT58L512L18FF-7.5IT
元件分类: SRAM
英文描述: 512K X 18 CACHE SRAM, 7.5 ns, PBGA165
封装: 13 X 15 MM, FBGA-165
文件页数: 13/27页
文件大小: 417K
代理商: MT58L512L18FF-7.5IT
20
8Mb: 512K x 18, 256K x 32/36 Flow-Through SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L512L18F_C.p65 – Rev. 2/02
2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
FLOW-THROUGH SYNCBURST SRAM
Figure 1
3.3V I/O OUTPUT LOAD EQUIVALENT
Q
50
V = 1.5V
Z = 50
O
T
Q
351
317
5pF
+3.3V
Figure 2
3.3V I/O OUTPUT LOAD EQUIVALENT
LOAD DERATING CURVES
Micron 512K x 18, 256K x 32, and 256K x 36 SyncBurst
SRAM timing is dependent upon the capacitive loading
on the outputs.
Consult the factory for copies of I/O current versus
voltage curves.
3.3V I/O AC TEST CONDITIONS
Input pulse levels ................. VIH = (VDD/2.2) + 1.5V
................... VIL = (VDD/2.2) - 1.5V
Input rise and fall times ..................................... 1ns
Input timing reference levels ..................... VDD/2.2
Output reference levels ............................ VDDQ/2.2
Output load ............................. See Figures 1 and 2
Q
50
V = 1.25V
Z = 50
O
T
Figure 3
2.5V I/O OUTPUT LOAD EQUIVALENT
Q
225
225
5pF
+2.5V
Figure 4
2.5V I/O OUTPUT LOAD EQUIVALENT
2.5V I/O AC TEST CONDITIONS
Input pulse levels ............. VIH = (VDD/2.64) + 1.25V
............... VIL = (VDD/2.64) - 1.25V
Input rise and fall times ..................................... 1ns
Input timing reference levels ................... VDD/2.64
Output reference levels ............................... VDDQ/2
Output load ............................. See Figures 3 and 4
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