- 您现在的位置：买卖IC网 > PDF目录187166 > MT58L512L18FF-7.5IT 512K X 18 CACHE SRAM, 7.5 ns, PBGA165 PDF资料下载
参数资料
| 型号： | MT58L512L18FF-7.5IT |
| 元件分类： | SRAM |
| 英文描述： | 512K X 18 CACHE SRAM, 7.5 ns, PBGA165 |
| 封装： | 13 X 15 MM, FBGA-165 |
| 文件页数： | 25/27页 |
| 文件大小： | 417K |
| 代理商： | MT58L512L18FF-7.5IT |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页当前第25页第26页第27页
7
8Mb: 512K x 18, 256K x 32/36 Flow-Through SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L512L18F_C.p65 – Rev. 2/02
2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
FLOW-THROUGH SYNCBURST SRAM
TQFP PIN DESCRIPTIONS
x18
x32/x36
SYMBOL
TYPE
DESCRIPTION
37
SA0
Input
Synchronous Address Inputs: These inputs are registered and must
36
SA1
meet the setup and hold times around the rising edge of CLK. Two
32-35, 44-50,
SA
different pinouts are available for the TQFP package.
80-82, 99,
81, 82, 99,
100
92 (T Version) 92 (T Version)
43 (S Version) 43 (S Version)
93
BWa#
Input
Synchronous Byte Write Enables: These active LOW inputs allow
94
BWb#
individual bytes to be written and must meet the setup and hold
–
95
BWc#
times around the rising edge of CLK. A byte write enable is LOW
–
96
BWd#
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQa pins and DQPa; BWb# controls DQb pins and
DQPb. For the x32 and x36 versions, BWa# controls DQa pins and
DQPa; BWb# controls DQb pins and DQPb; BWc# controls DQc pins
and DQPc; BWd# controls DQd pins and DQPd. Parity is only
available on the x18 and x36 versions.
87
BWE#
Input
Byte Write Enable: This active LOW input permits BYTE WRITE
operations and must meet the setup and hold times around the
rising edge of CLK.
88
GW#
Input
Global Write: This active LOW input allows a full 18-, 32- or 36-bit
WRITE to occur independent of the BWE# and BWx# lines and must
meet the setup and hold times around the rising edge of CLK.
89
CLK
Input
Clock: CLK registers address, data, chip enable, byte write enables
and burst control inputs on its rising edge. All synchronous inputs
must meet setup and hold times around the clock’s rising edge.
98
CE#
Input
Synchronous Chip Enable: This active LOW input is used to enable
the device and conditions the internal use of ADSP#. CE# is sampled
only when a new external address is loaded.
92 (S Version) 92 (S Version)
CE2#
Input
Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded. CE2# is only available on the S Version.
97
CE2
Input
Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loaded.
86
OE#
Input
Output Enable: This active LOW, asynchronous input enables the
data I/O output drivers.
83
ADV#
Input
Synchronous Address Advance: This active LOW input is used to
advance the internal burst counter, controlling burst access after
the external address is loaded. A HIGH on this pin effectively causes
wait states to be generated (no address advance). To ensure use of
correct address during a WRITE cycle, ADV# must be HIGH at the
rising edge of the first clock after an ADSP# cycle is initiated.
85
ADSC#
Input
Synchronous Address Status Controller: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ or WRITE is performed using the new address if
CE# is LOW. ADSC# is also used to place the chip into power-down
state when CE# is HIGH.
相关PDF资料 |
PDF描述 |
|---|---|
| MT58LC32K36B3LG-10 | 32K X 36 STANDARD SRAM, 10 ns, PQFP100 |
| MT58LC64K18D8LG-15 | 64K X 18 STANDARD SRAM, 7 ns, PQFP100 |
| MT5C1001C-35LE/883C | 1M X 1 STANDARD SRAM, 35 ns, CDIP28 |
| MT5C1001F-55LE/883C | 1M X 1 STANDARD SRAM, 55 ns, CDFP32 |
| MT5C1005C-35/IT | STANDARD SRAM, CDIP28 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT58L512L18FF-8.5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT58L512L18FS-10 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT58L512L18FS-10IT | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel 制造商:Micron Technology Inc 功能描述: |
| MT58L512L18FS-8.5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT58L512L18FT-10 | 制造商:Cypress Semiconductor 功能描述:512KX18 SRAM PLASTIC TQFP 3.3V 制造商:Rochester Electronics LLC 功能描述:- Bulk |
发布紧急采购，3分钟左右您将得到回复。