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参数资料
| 型号： | MT58L512L18FF-7.5IT |
| 元件分类： | SRAM |
| 英文描述： | 512K X 18 CACHE SRAM, 7.5 ns, PBGA165 |
| 封装： | 13 X 15 MM, FBGA-165 |
| 文件页数： | 21/27页 |
| 文件大小： | 417K |
| 代理商： | MT58L512L18FF-7.5IT |
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3
8Mb: 512K x 18, 256K x 32/36 Flow-Through SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L512L18F_C.p65 – Rev. 2/02
2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
FLOW-THROUGH SYNCBURST SRAM
GENERAL DESCRIPTION (continued)
enables (BWx#) and global write (GW#). Note that
CE2# is not available on the T Version.
Asynchronous inputs include the output enable (OE#),
clock (CLK) and snooze enable (ZZ). There is also a burst
mode input (MODE) that selects between interleaved
and linear burst modes. The data-out (Q), enabled by
OE#, is also asynchronous. WRITE cycles can be from
one to two bytes wide (x18) or from one to four bytes wide
(x32/x36), as controlled by the write control inputs.
Burst operation can be initiated with either address
status processor (ADSP#) or address status controller
(ADSC#) inputs. Subsequent burst addresses can be in-
ternally generated as controlled by the burst advance
input (ADV#).
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes to
be written. During WRITE cycles on the x18 device, BWa#
controls DQa pins and DQPa; BWb# controls DQb pins
and DQPb. During WRITE cycles on the x32 and x36
devices, BWa# controls DQa pins and DQPa; BWb#
controls DQb pins and DQPb; BWc# controls DQc pins
and DQPc; BWd# controls DQd pins and DQPd. GW#
LOW causes all bytes to be written. Parity bits are only
available on the x18 and x36 versions.
Micron’s 8Mb SyncBurst SRAMs operate from a +3.3V
VDD power supply, and all inputs and outputs are TTL-
compatible. Users can choose either a 3.3V or 2.5V I/O
version. The device is ideally suited for 486, Pentium,
680x0 and PowerPC systems and those systems that ben-
efit from a wide synchronous data bus. The device is also
ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-wide
applications.
Please refer to Micron’S Web site (www.micron.com/
sramds) for the latest data sheet.
TQFP PINOUTS
At the time of the writing of this data sheet, there are
two pinouts in the industry. Micron will support both
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT58L512L18FF-8.5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT58L512L18FS-10 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT58L512L18FS-10IT | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel 制造商:Micron Technology Inc 功能描述: |
| MT58L512L18FS-8.5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT58L512L18FT-10 | 制造商:Cypress Semiconductor 功能描述:512KX18 SRAM PLASTIC TQFP 3.3V 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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